Successive approximation register analog-to-digital converter

1. A method of an electronic system, comprising:

receiving a radio frequency (RF) signal with an analog front end of the electronic system;

converting an output of the analog front end to a digital representation of the received RF signal using a successive approximation register (SAR) analog-to-digital converter (ADC) of a digital front end of the electronic system; and

demodulating the digital representation, with the digital front end, to obtain a baseband signal for baseband processing circuitry of the electronic system;

wherein said converting comprises varying a settling time of the SAR ADC in response to a bit position of a digital output code being determined by the SAR ADC.

2. The method of claim 1 , wherein said varying comprises selecting the settling time for a digital-to-analog converter of the SAR ADC based on the bit position of the digital output code being determined.

3. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for a most significant bit of the digital output code than for a least significant bit of the digital output code.

4. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for a most significant bit of the digital output code than for a second most significant bit of the digital output code.

5. The method of claim 2 , wherein said selecting comprises selecting a greater settling time for one bit of the digital output code than for another bit of the digital output code, wherein the one bit is a more significant bit than the another bit.

6. The method of claim 2 , wherein said selecting comprises adjusting a time constant of an RC circuit to obtain the selected settling time.

7. The method of claim 2 , wherein said selecting comprises adjusting an effective resistance value of an RC circuit to obtain the selected settling time.

8. The method of claim 2 , wherein said selecting comprises adjusting an effective capacitance value of an RC circuit to obtain the selected settling time.

9. The method of claim 2 , further comprising:

comparing an analog reference value generated by the digital-to-analog converter in response to expiration of the selected settling time for the digital-to-analog converter; and

updating the bit position of the digital output code based on a comparison result of said comparing.

10. The method of claim 9 , wherein said updating comprises updating a bit position after expiration of a comparator settling time.

11. The method of claim 9 , further comprising:

providing the digital-to-analog converter with a digital reference code that corresponds to an approximation of the analog input value; and

generating the analog reference value with the digital-to-analog converter based upon the digital reference code.

12. An apparatus, comprising:

an analog front end configured to receive a radio frequency (RF) signal;

a digital front end comprising a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an output of the analog front end to a digital representation of the received RF signal, wherein the digital front end is configured to demodulate the digital representation to obtain a baseband signal; and

baseband processing circuitry configured to process the baseband signal;

wherein, in response to converting the output of the analog front end, said SAR ADC is configured to vary a settling time of the SAR ADC based on a bit position of a digital output code being determined by the SAR ADC.

13. The apparatus of claim 12 , wherein the SAR ADC comprises:

a digital-to-analog converter configured to generate an analog reference value based on a received digital reference value;

a comparator configured to compare an analog input value to the output of the analog front end after expiration of the settling time for the digital-to-analog converter and generate a comparison result indicative of a relationship between the output of the analog front end and the analog reference value; and

control logic circuitry configured to select the settling time for the digital-to-analog converter based on the bit position of the digital output code to be determined.

14. The apparatus of claim 13 , wherein said control logic circuitry is configured to select a greater settling time for a most significant bit of the digital output code than for a least significant bit of the digital output code.

15. The apparatus of claim 13 , wherein said control logic circuitry is configured to select a greater settling time for a most significant bit of the digital output code than for a second most significant bit of the digital output code.

16. The apparatus of claim 13 , wherein said control logic circuitry is configured to select a greater settling time for one bit of the digital output code than for another bit of the digital output code, wherein the one bit is a more significant bit than the another bit.

17. The apparatus of claim 13 , wherein:

the SAR ADC further includes an RC circuit; and

the control circuitry is configured to adjust a time constant of an RC circuit to obtain the selected settling time.

18. The apparatus of claim 13 , wherein:

the comparator is further configured to sample the output of the analog front end after expiration of the settling time; and

the control logic circuitry is further configured to update the bit position a comparator settling time after the comparator samples the output of the analog front end.

19. The apparatus of claim 13 , wherein the control logic circuitry is further configured to update the bit position after expiration of a uniform comparator settling time.