IP Library › Granted Patent US 11,068,778
Granted Patent B2
US 11,068,778 · App. 15/152,073 · Granted Jul 20, 2021

System and method for optimizing the design of circuit traces in a printed circuit board for high speed communications

Inventors: Chun-Li Liao (Taipei, TW); Bhyrav M. Mutnury (Round Rock, TX); Ching Huei (Carol) Chen (Pingtun, TW); Nick Lee (Taipei, TW)
Assignee: Dell Products L.P.
G06N3/08G06F30/394
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Quick Facts
Patent No.
US 11,068,778
App. No.
15/152,073
Filed
May 11, 2016
Granted
Jul 20, 2021
Kind
B2
Art Unit
2121
USPC
706/19
Abstract

A method includes training an artificial neural network with training data that comprises a sets of design parameter values for design parameters for circuit traces in a high speed communication link, determining an output formula that relates a sets of design parameters to a corresponding output parameter for the circuit traces in response to training the artificial neural network, running the output formula using a second set of design parameter values to obtain a corresponding set of output parameters for the circuit traces, determining that the corresponding set of output parameters differ from a set of modeled output parameters by less than a predefined percentage, and fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage.

Claims (269)

1. A method, comprising:

training an artificial neural network with first training data, wherein the first training data includes a first plurality of sets of design parameter values for a plurality of design parameters for circuit traces in a high speed communication link, wherein the artificial neural network provides an output given as:

y

=

f

⁡

(

x

)

=

∑

j

=

1

M

⁢

⁢

k

j

*

G

⁡

(

∑

i

=

1

N

⁢

w

ij

,

x

i

+

b

j

)

+

d

,

and

⁢

⁢

G

⁡

(

x

)

=

2

1

+

e

-

2

⁢

x

-

1

where N is a number of inputs, M is a number of hidden nodes, x is an input vector, w ij is a weight connecting a i th input layer node to a j th hidden layer node, k j is a weight connecting the j th hidden layer node to an output layer node, and b j , e and d are constants, wherein the training is based upon a d-optimal training algorithm, and wherein training the artificial neural network includes providing a particular one of the design parameters to an associated one of the inputs;

determining, in response to training the artificial neural network, an output formula that relates a particular set of the sets of design parameters to a corresponding output of the artificial neural network, wherein each output is associated with a particular output parameter for the circuit traces;

running the output formula using a second plurality of sets of design parameter values for the design parameters to obtain a corresponding set of output parameters for the circuit traces;

determining that the corresponding set of output parameters for the circuit traces differ from a set of modeled output parameters by less than a predefined percentage; and

fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage;

wherein the design parameter values comprise:

a trace width of a first trace and a second trace of a trace pair of the printed circuit board;

a trace thickness of the first trace and the second trace;

a trace spacing between the first trace and the second trace;

a trace distance between the first trace pair and a second trace pair of the printed circuit board;

a surface roughness of the first trace and the second trace;

a height of a substrate of the printed circuit board;

a dielectric constant of the substrate;

a loss tangent of the substrate;

a dielectric constant of a mask layer of the printed circuit board; and

a loss tangent of the mask layer; and

wherein the output parameters comprise:

a channel impedance of the first trace pair;

a channel loss of the first trace pair;

a near-end crosstalk of the first trace pair; and

a far-end crosstalk of the first trace pair.

2. The method of claim 1 , further comprising:

selecting the first training data, wherein training the artificial neural network is in response to selecting the first training data.

3. The method of claim 2 , wherein in selecting the first training data, the method further comprises:

using an optimization model to determine a number of sets of design parameter values in the first plurality of sets of design parameter values.

4. The method of claim 1 , wherein in training the artificial neural network, the method further comprises:

training the artificial neural network to maximize a determinant of an information matrix of the plurality of sets of the design parameter values.

5. The method of claim 1 , further comprising:

training the artificial neural network with second training data, wherein the second training data comprises a second plurality of sets of design parameter values for the plurality of design parameters for the circuit traces in response to determining that the corresponding set of output parameters for the circuit traces does not differ from a set of modeled output parameters by less than a predefined percentage.

6. A non-transitory computer-readable medium including code for performing a method, the method comprising:

training an artificial neural network with first training data, wherein the first training data comprises a first plurality of sets of design parameter values for a plurality of design parameters for circuit traces in a high speed communication link, wherein the artificial neural network provides an output given as:

y

=

f

⁡

(

x

)

=

∑

j

=

1

M

⁢

⁢

k

j

*

G

⁡

(

∑

i

=

1

N

⁢

w

ij

,

x

i

+

b

j

)

+

d

,

and

⁢

⁢

G

⁡

(

x

)

=

2

1

+

e

-

2

⁢

x

-

1

where N is a number of inputs, M is a number of hidden nodes, x is an input vector, w ij is a weight connecting a i th input layer node to a j th hidden layer node, k j is a weight connecting the j th hidden layer node to an output layer node, and b j , e and d are constants, wherein the training is based upon a d-optimal training algorithm, and wherein training the artificial neural network includes providing a particular one of the design parameters to an associated one of the inputs;

determining, in response to training the artificial neural network, an output formula that relates a particular set of the sets of design parameters to a corresponding output of the artificial neural network, wherein each output is associated with a particular output parameter for the circuit traces;

running the output formula using a second plurality of sets of design parameter values for the design parameters to obtain a corresponding set of output parameters for the circuit traces;

determining that the corresponding set of output parameters for the circuit traces differ from a set of modeled output parameters by less than a predefined percentage; and

fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage;

wherein the design parameter values comprise:

a trace width of a first trace and a second trace of a trace pair of the printed circuit board;

a trace thickness of the first trace and the second trace;

a trace spacing between the first trace and the second trace;

a trace distance between the first trace pair and a second trace pair of the printed circuit board;

a surface roughness of the first trace and the second trace;

a height of a substrate of the printed circuit board;

a dielectric constant of the substrate;

a loss tangent of the substrate;

a dielectric constant of a mask layer of the printed circuit board; and

a loss tangent of the mask layer; and

wherein the output parameters comprise:

a channel impedance of the first trace pair;

a channel loss of the first trace pair;

a near-end crosstalk of the first trace pair; and

a far-end crosstalk of the first trace pair.

7. The computer-readable medium of claim 6 , the method further comprising:

selecting the first training data, wherein training the artificial neural network is in response to selecting the first training data.

8. The computer-readable medium of claim 7 , wherein in selecting the first training data, the method further comprises:

using an optimization model to determine a number of sets of design parameter values in the first plurality of sets of design parameter values.

9. The computer-readable medium of claim 6 , wherein in training the artificial neural network, the method further comprises:

training the artificial neural network to maximize a determinant of an information matrix of the plurality of sets of the design parameter values.

10. The computer-readable medium of claim 6 , the method further comprising:

training the artificial neural network with second training data, wherein the second training data comprises a second plurality of sets of design parameter values for the plurality of design parameters for the circuit traces in response to determining that the corresponding set of output parameters for the circuit traces does not differ from a set of modeled output parameters by less than a predefined percentage.

11. An information handling system, comprising:

a memory that stores code; and

a processor that executes code stored in memory to:

train an artificial neural network with first training data, wherein the first training data comprises a first plurality of sets of design parameter values for a design parameters for circuit traces in a high speed communication link, wherein the artificial neural network provides an output given as:

y

=

f

⁡

(

x

)

=

∑

j

=

1

M

⁢

⁢

k

j

*

G

⁡

(

∑

i

=

1

N

⁢

w

ij

,

x

i

+

b

j

)

+

d

,

and

⁢

⁢

G

⁡

(

x

)

=

2

1

+

e

-

2

⁢

x

-

1

where N is a number of inputs, M is a number of hidden nodes, x is an input vector, w ij is a weight connecting a i th input layer node to a j th hidden layer node, k j is a weight connecting the j th hidden layer node to an output layer node, and b j , e and d are constants, wherein the training is based upon a d-optimal training algorithm, and wherein training the artificial neural network includes providing a particular one of the design parameters to an associated one of the inputs;

determine, in response to training the artificial neural network, an output formula that relates a particular set of the sets of design parameters to a corresponding output of the artificial neural network, wherein each output is associated with a particular output parameter for the circuit traces;

run the output formula using a second plurality of sets of design parameter values for the plurality of design parameters to obtain a corresponding set of output parameters for the circuit traces;

determine that the corresponding set of output parameters for the circuit traces differ from a set of modeled output parameters by less than a predefined percentage; and

fabricate a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage;

wherein the design parameter values comprise:

a trace width of a first trace and a second trace of a trace pair of the printed circuit board;

a trace thickness of the first trace and the second trace;

a trace spacing between the first trace and the second trace;

a trace distance between the first trace pair and a second trace pair of the printed circuit board;

a surface roughness of the first trace and the second trace;

a height of a substrate of the printed circuit board;

a dielectric constant of the substrate;

a loss tangent of the substrate;

a dielectric constant of a mask layer of the printed circuit board; and

a loss tangent of the mask layer; and

wherein the output parameters comprise:

a channel impedance of the first trace pair;

a channel loss of the first trace pair;

a near-end crosstalk of the first trace pair; and

a far-end crosstalk of the first trace pair.

12. The information handling system of claim 11 , wherein the processor is further to:

select the first training data, wherein training the artificial neural network is in response to selecting the first training data.

13. The information handling system of claim 12 , wherein in selecting the first training data, the processor is further to:

use an optimization model to determine a number of sets of design parameter values in the first plurality of sets of design parameter values.

14. The information handling system of claim 11 , wherein in training the artificial neural network, the processor is further to:

train the artificial neural network to maximize a determinant of an information matrix of the plurality of sets of the design parameter values.

15. The information handling system of claim 11 , wherein the processor is further to:

train the artificial neural network with second training data, wherein the second training data comprises a second plurality of sets of design parameter values for the plurality of design parameters for the circuit traces in response to determining that the corresponding set of output parameters for the circuit traces does not differ from a set of modeled output parameters by less than a predefined percentage.

Assignments (15)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061753/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC
Reel/Frame 061324/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058216/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040134/0001 →
SECURITY AGREEMENT Recorded Sep 21, 2016
From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040136/0001 →
RELEASE OF SEC. INT. IN PATENTS (NOTES) Recorded Sep 14, 2016
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040026/0710 →
RELEASE OF SEC. INT. IN PATENTS (TL) Recorded Sep 14, 2016
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040027/0329 →
RELEASE OF SEC. INT. IN PATENTS (ABL) Recorded Sep 13, 2016
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040013/0733 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (ABL) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 039643/0953 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (TERM LOAN) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 039719/0889 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (NOTES) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 039644/0084 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2016
From: LIAO, CHUN-LI; MUTNURY, BHYRAV M.; CHEN, CHING HUEI (CAROL); LEE, NICK
To: DELL PRODUCTS, LP
Reel/Frame 039029/0073 →
Continuity (1)
Related Publication 20170330072A1 · Nov 16, 2017