Apparatus for correcting gain error of analog-to-digital converter

1. A bias generator comprising:

an operational amplifier including a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal;

a resister string including at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, suitable for generating bias voltages; and

a control circuit coupled between the second input terminal and the resister string, suitable for swapping the offset voltage, and selectively providing the offset voltage and a swapped offset voltage to the second input terminal of the operational amplifier in accordance with a swap control signal, wherein the swapped offset voltage and the offset voltage have a same voltage value with opposite polarities.

2. The bias generator of claim 1 , wherein the bias voltages include a low bias voltage and a high bias voltage.

3. The bias generator of claim 2 , wherein the resister string includes:

a first resister coupled between the ground terminal and a first node for outputting the low bias voltage;

a second resister coupled between the first node and a second node; and

a third resister coupled between the second node and a third node for outputting the high bias voltage, the third node coupled to the output terminal of the operational amplifier.

4. The bias generator of claim 3 , wherein the control circuit includes:

a first group of switches suitable for providing the offset voltage to the second input terminal in response to a first swap control signal; and

a second group of switches suitable for providing the swapped offset voltage to the second input terminal in response to a second swap control signal.

5. An apparatus comprising:

an analog-to-digital converter (ADC); and

a bias generator suitable for providing bias voltages to the ADC, comprising:

an operational amplifier including a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal;

a resister string including at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, suitable for generating the bias voltages; and

a control circuit coupled between the second input terminal and the resister string, suitable for swapping the offset voltage, and selectively providing the offset voltage and a swapped offset voltage to the second input terminal of the operational amplifier in accordance with a swap control signal, wherein the swapped offset voltage and the offset voltage have a same voltage value with opposite polarities.

6. The apparatus of claim 5 , wherein the bias voltages include a low bias voltage and a high bias voltage.

7. The apparatus of claim 6 , wherein the resister string includes:

a first resister coupled between the ground terminal and a first node for outputting the low bias voltage;

a second resister coupled between the first node and a second node; and

a third resister coupled between the second node and a third node for outputting the high bias voltage, the third node coupled to the output terminal of the operational amplifier.

8. The apparatus of claim 7 , wherein the control circuit includes:

a first group of switches suitable for providing the offset voltage to the second input terminal in response to a first swap control signal; and

a second group of switches suitable for providing the swapped offset voltage to the second input terminal in response to a second swap control signal.

9. The apparatus of claim 5 , wherein the ADC includes one of a successive-approximation-resister ADC and a sigma-delta ADC.

10. A method for operating a bias generator including an operational amplifier having a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal, and a resister string including at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, comprising:

swapping the offset voltage; and

selectively providing the offset voltage and a swapped offset voltage to the second input terminal of the operational amplifier in accordance with a swap control signal, wherein the swapped offset voltage and the offset voltage have a same voltage value with opposite polarities.

11. The method of claim 10 , wherein the bias voltages include a low bias voltage and a high bias voltage.

12. The method of claim 11 , wherein providing the offset voltage and the swapped offset voltage to the second input terminal of the operational amplifier alternatively comprises providing the offset voltage to the second input terminal in response to a first swap control signal, and providing the swapped offset voltage to the second input terminal in response to a second swap control signal.

13. A method for operating an analog-to-digital converter (ADC) provided bias voltages from a bias generator including an operational amplifier having a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal, and a resister string including at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, comprising:

receiving, from the bias generator, a first bias voltage, generated based on the offset voltage in response to a first swap control signal; and

receiving, from the bias generator, a second bias voltage generated based on a swapped offset voltage in response to a second swap control signal, wherein the swapped offset voltage and the offset voltage have a same voltage value and opposite polarities.

14. The method of claim 13 , wherein each of the first and second bias voltages include a low bias voltage and a high bias voltage.

15. The method of claim 13 , further comprising:

performing a first data output based on the first bias voltage;

performing a second data output based on the second bias voltage; and

averaging the first data output and the second data output.