IP Library Granted Patent US 9,954,448
Granted Patent B2
US 9,954,448 · App. 15/155,909 · Granted Apr 24, 2018

Current mode regulator

Inventors: Ross E. Teggatz (Plano, TX); David Briggs (Plano, TX); Amer H. Atrash (Plano, TX); Wayne T. Chen (Plano, TX)
Assignee: TRIUNE SYSTEMS, LLC
H02M3/33507H02M1/08H02M1/14H02M1/42H02M3/3387H02M1/4225H02M2001/0006H02M2001/0009H02M2001/0032Y02B70/126Y02B70/16
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Quick Facts
Patent No.
US 9,954,448
App. No.
15/155,909
Granted
Apr 24, 2018
Kind
B2
Abstract

Disclosed are advances in the arts with novel and useful current mode regulators. Circuits, systems, and methods for current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.

Claims (34)

1. A circuit comprising:

a current monitor at an output node configured to compare an output signal to a reference;

a first isolated communication link configured to provide feedback from the monitored output node to a primary side of a current mode regulator; and

a second isolated communication link configured to provide the feedback from the monitored output node to a fly-back regulator.

2. The circuit of claim 1 wherein the primary side is configured to receive an input signal at an input node.

3. The circuit of claim 1 further comprising a secondary side isolated from the primary side and configured to receive a signal from the primary side.

4. The circuit of claim 1 wherein the current mode regulator comprises the primary side and a secondary side, and is configured to rectify an input signal and to provide the rectified input signal to the output node.

5. The circuit of claim 1 wherein the current mode regulator is configured to use the feedback to regulate the signal provided to the output node.

6. An electronic system comprising:

a current mode regulator having a primary side configured to receive an input signal at an input node, the primary side operably coupled to:

a secondary side configured to receive a signal from the primary side, the secondary side having an output node for outputting an output signal; and

an isolated communication link configured to provide feedback from the output node to the primary side of a first regulator; and

a stand-by power supply comprising a second isolated communication link configured to provide feedback from the output node to the primary side of a second regulator.

7. The electronic system of claim 6 wherein the first regulator spans the primary side and the secondary side and is configured to rectify the input signal and to provide the rectified input signal to the output node.

8. The electronic system of claim 6 further comprising a current monitor at the output node configured to compare the output signal to a reference.

9. The electronic system of claim 6 wherein the first regulator is configured to use the feedback to regulate a signal provided to the output node.

10. The electronic circuit of claim 6 further comprising a second regulator operably coupled to a primary side voltage.

11. The electronic circuit of claim 6 further comprising a standby regulator, wherein the stand-by power supply is adapted to be responsive to feedback passed from the stand-by regulator to a second regulator through the communication link.

12. A method for current mode regulation comprising:

maintaining isolation between a primary side and a secondary side with a first isolation circuit;

providing feedback from a monitored output node to the primary side;

providing second feedback through a second isolation circuit to a flyback regulator; and

regulating a signal provided to the output node using the feedback.

13. The method of claim 12 further comprising receiving an input signal at an input node to a primary side and generating the signal provided to the output node using the input signal.

14. The method of claim 12 further comprising:

receiving an input signal at an input node to a primary side;

rectifying the input signal; and

regulating the transfer of the rectified signal to the isolated secondary side.

15. The method of claim 12 further comprising:

receiving an input signal at an input node to a primary side;

rectifying the input signal;

regulating the transfer of the rectified signal to the isolated secondary side; and

transferring the rectified secondary side signal to the output node.

16. The method of claim 12 further comprising comparing the signal at the output node with a reference to generate the feedback.

Assignments (3)
ASSIGNMENT OF PATENT SECURITY INTEREST PREVIOUSLY RECORDED AT REEL/FRAME (040646/0799) Recorded Feb 17, 2023
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS RESIGNING AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 062781/0544 →
SECURITY INTEREST Recorded Nov 17, 2016
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.; SEMTECH EV, INC.; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 040646/0799 →
SECURITY INTEREST Recorded Jul 15, 2016
From: TRIUNE IP, LLC
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039170/0103 →
Continuity (3)
Continuation 13567039 · Aug 4, 2012
Provisional Application 61515782 · Aug 5, 2011
Related Publication 20160261197A1 · Sep 8, 2016