IP Library Granted Patent US 10,348,335
Granted Patent B2
US 10,348,335 · App. 15/156,088 · Granted Jul 9, 2019

Miscorrection avoidance for turbo product codes

Inventors: Aman Bhatia (San Jose, CA); Naveen Kumar (San Jose, CA); Yi-Min Lin (San Jose, CA); Lingqi Zeng (San Jose, CA)
Assignee: SK hynix Inc.
H03M13/2963G06F11/1012H03M13/2912H03M13/2921H03M13/618H03M13/152
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Quick Facts
Patent No.
US 10,348,335
App. No.
15/156,088
Granted
Jul 9, 2019
Kind
B2
Abstract

Systems may include a memory storage suitable for storing data, an encoder suitable for encoding data into codewords arranged in an array of a number of rows and a number of columns, and a decoder suitable for receiving the encoded codewords, decoding the encoded codewords, and detecting miscorrections in the decoding.

Claims (42)

1. A system, comprising:

a memory storage configured to store data;

an encoder configured to encode data into codewords, the data comprising bits arranged in an array of a number of rows and a number of columns, the encoder further configured to compute a first parity of the codewords, the first parity comprising X bits, where X is the number of bits in each of N row-column intersections of the array, each of the X bits of the first parity being computed based on N position-wise bits of the respective N row-column intersections; and

a decoder configured to

receive the encoded codewords,

decode the encoded codewords to generate a decoded result that includes a second parity computed by the decoder, and

detect whether the decoded result is incorrect by determining whether the first parity computed by the encoder matches the second parity computed by the decoder.

2. The system of claim 1 , wherein the encoder is further configured to shorten bits along a diagonal of the array.

3. The system of claim 2 , wherein the encoder is further configured to shorten bits on the diagonal of the array by zero-padding the bits along the diagonal.

4. The system of claim 1 , wherein the first parity computed by the encoder includes a first N-bit XOR parity, each of the N-bits being computed by taking the XOR of the N position-wise bits of the respective N row-column intersections, and

wherein the second parity computed by the decoder includes a second N-bit XOR parity of the codewords arranged in the array.

5. The system of claim 4 , wherein to detect whether the decoded result is incorrect the decoder determines whether the first XOR parity computed by the encoder matches the second XOR parity computed by the decoder.

6. The system of claim 4 , wherein the encoder is further configured to store the computed first XOR parity in the array.

7. The system of claim 1 , wherein the encoder is further configured to permute bits at intersections between the number of rows and the number of columns prior to encoding to column codewords.

8. A memory device, comprising:

an encoder configured to encode data into codewords, the data comprising bits arranged in an array of a number of rows and a number of columns, the encoder further configured to compute a first parity of the codewords, the first parity comprising X bits, where X is the number of bits in each of N row-column intersections of the array, each of the X bits of the first parity being computed based on N position-wise bits of the respective N row-column intersections; and

a decoder configured to

receive the encoded codewords,

decode the encoded codewords to generate a decoded result that includes a second parity computed by the decoder, and

detect whether the decoded result is correct by determining whether the first parity computed by the encoder matches the second parity computed by the decoder.

9. The memory device of claim 8 , wherein the encoder is further configured to shorten bits along a diagonal of the array.

10. The memory device of claim 9 , wherein the encoder is further configured to shorten bits by zero-padding the bits along the diagonal.

11. The memory device of claim 8 , wherein the first parity computed by the encoder includes a first N-bit XOR parity, each of the N-bits being computed by taking the XOR of the N position-wise bits of the respective N row-column intersections, and

wherein the second parity computed by the decoder includes a second N-bit XOR parity of the codewords arranged in the array.

12. The memory device of claim 11 , wherein to detect whether the decoded result is incorrect the decoder determines whether the first XOR parity computed by the encoder matches the second XOR parity computed by the decoder.

13. The memory device of claim 11 , wherein the encoder is further configured to store the computed first XOR parity in the array.

14. The memory device of claim 8 , wherein the encoder is further configured to permute bits at intersections between the number of rows and the number of columns prior to encoding to column code words.

15. A method, comprising:

encoding, with an encoder, data into codewords, the data comprising bits arranged in an array of a number of rows and a number of columns, and computing with the encoder a first parity of the codewords, the first parity comprising X bits, where X is the number of bits in each of N row-column intersections of the array, each of the X bits of the first parity being computed based on N position-wise bits of the respective N row-column intersections;

receiving, with a decoder, the encoded codewords;

decoding, with the decoder, the received codewords to generate a decoded result that includes a second parity computed with the decoder; and

detecting, with the decoder, whether the decoded result is incorrect by determining whether the first parity computed by the encoder matches the second parity computed by the decoder.

16. The method of claim 15 , further comprising shortening bits along a diagonal of the array.

17. The method of claim 16 , wherein

the computing the first parity, with the encoder, includes computing a first N-bit XOR parity, each of the N-bits being computed by taking the XOR of the N position-wise bits of the respective N row-column intersections; and

the computing the second parity, with the decoder, includes computing a second N-bit XOR parity of the codewords arranged in the array.

18. The method of claim 17 , wherein the detecting whether the decoded result is correct, with the decoder, includes determining whether the first XOR parity computed with the encoder matches the second XOR parity computed with the decoder.

19. The method of claim 16 , further comprising permuting, with the encoder, bits at intersections between the number of rows and the number of columns.

20. The method of claim 19 , wherein

the computing the first parity, with the encoder, includes computing a first N-bit XOR parity, each of the N-bits being computed by taking the XOR of the N position-wise bits of the respective N row-column intersections; and

the computing the second parity, with the decoder, includes computing a second N-bit XOR parity of the codewords arranged in the array;

wherein the detecting whether the decoded result is incorrect, with the decoder, includes determining whether the first N-bit XOR parity computed with the encoder matches the second N-bit XOR parity computed with the decoder.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2019
From: BHATIA, AMAN; KUMAR, NAVEEN; LIN, YI-MIN; ZENG, LINGQI
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 049255/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
Continuity (2)
Provisional Application 62162511 · May 15, 2015
Related Publication 20160336969A1 · Nov 17, 2016