Seal ring structure to avoid delamination defect
View Patent ↗A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices. The seal ring structure includes a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers. Each of the hollow through-hole structure within an interlayer dielectric layer includes a through-hole disposed within one of the interlayer dielectric layers, a diffusion barrier layer formed at the bottom, sidewalls and the top of the through-hole, and a seed layer disposed on the diffusion barrier layer. The diffusion barrier layer and the seed layer cover the top of the through-hole so that the through-hole has a void to form the hollow through-hole structure.
1. A semiconductor device comprising:
a semiconductor substrate;
a plurality of integrated circuit (IC) devices on the semiconductor substrate; and
a seal ring structure surrounding each one of the integrated circuit devices, the seal ring structure comprising a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers.
2. The semiconductor device of claim 1 , wherein a hollow through-hole structure comprises a through-hole disposed within one of the interlayer dielectric layers, a diffusion barrier layer and a seed layer sequentially disposed in this order at a bottom portion and sidewalls of the through-hole and sealing an opening at a top portion of the through-hole.
3. The semiconductor device of claim 2 , wherein a sum of a thickness of the diffusion barrier layer and a thickness of the seed layer is less than a radius of the through-hole.
4. The semiconductor device of claim 2 , wherein the diffusion barrier layer comprises at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, tungsten nitride, an alloy thereof, and a compound thereof.
5. The semiconductor device of claim 2 , wherein the seed layer is a copper seed layer.
6. The semiconductor device of claim 1 , wherein a through-hole structure comprises a critical dimension less than 45 nm.
7. The semiconductor device of claim 1 , wherein the interlayer dielectric layers comprise a low-k material.
8. The semiconductor device of claim 1 , wherein the seal ring structure comprises:
a multi-layer metal interconnect structure disposed on opposite sides of the seal ring structure; and
a test pad disposed on the multi-layer metal interconnect structure.
9. An electronic apparatus comprising a semiconductor device including a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices, wherein the seal ring structure comprises a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers.
10. The electronic apparatus of claim 9 , wherein a hollow through-hole structure comprises a through-hole disposed within one of the interlayer dielectric layers, a diffusion barrier layer formed at a bottom and sidewalls and a top of the through-hole, and a seed layer disposed on the diffusion barrier layer.
11. The electronic apparatus of claim 10 , wherein a sum of a thickness of the diffusion barrier layer and a thickness of the seed layer is less than a radius of the through-hole.
12. The electronic apparatus of claim 10 , wherein the diffusion barrier layer comprises at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten, tungsten nitride, an alloy thereof, and a compound thereof.
13. The electronic apparatus of claim 10 , wherein the seed layer is a copper seed layer.