Performance optimization in soft decoding for turbo product codes

1. A system for performing turbo product code (TPC) decoding, comprising:

a memory device:

a processor; and

a non-transitory computer readable storage medium coupled to the processor, embedding computer program products executed by the processor, including computer instructions configured to:

control the memory device including

a solid state storage, and

a read controller coupled with the solid state storage, wherein the read controller comprises:

an error intersection identifier configured to:

determine a set of one or more error intersections using a set of error-containing codewords, and

update, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of one or more error intersections to obtain an updated set of one or more error intersections, wherein the Chase decoding is decoding upon combinatorically flipping certain least reliable bits;

a bit location selector configured to:

select from the set of one or more error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords; and

a decoder configured to:

perform the Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

2. The system of claim 1 , wherein a number of erroneous bits in the set of least reliable bit locations is less than a correction capability of the system plus the second value.

3. The system of claim 2 , wherein the number of erroneous bits is at least equal to the second value.

4. The system of claim 1 , wherein the Chase decoder performs the Chase decoding in at least an initial iteration and a subsequent iteration.

5. The system of claim 4 , wherein the first value is increased at the subsequent iteration.

6. The system of claim 4 , wherein the second value is decreased at the subsequent iteration.

7. A method for performing turbo product code (TPC) decoding in a memory device including an error intersection identifier, a bit location selector and a decoder, comprising:

determining, with the error intersection identifier, a set of one or more error intersections using a set of error-containing codewords;

updating, with the error intersection identifier, the set of one or more error intersections based at least in part on Chase decoding performed on the set of error-containing codewords to obtain an updated set of one or more error intersections, wherein the Chase decoding is decoding upon combinatorically flipping certain least reliable bits;

selecting, with the bit location selector, from the set of error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords; and

performing the Chase decoding, with the decoder, on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

8. The method of claim 7 , wherein a number of erroneous bits in the set of least reliable bit locations is less than a correction capability plus the second value.

9. The method of claim 8 , wherein the number of erroneous bits is at least equal to the second value.

10. The method of claim 7 , wherein the decoder performs the Chase decoding in at least an initial iteration and a subsequent iteration.

11. The method of claim 10 , wherein the first value is increased at the subsequent iteration.

12. The method of claim 10 , wherein the second value is decreased at the subsequent iteration.

13. A memory device for performing turbo product code (TPC) decoding, comprising:

a solid state storage; and

a read controller coupled with the solid state storage, wherein the read controller comprises:

an error intersection identifier configured to:

determine a set of one or more error intersections using a set of error-containing codewords; and

update, based at least in part on Chase decoding performed on the set of error-containing codewords, the set of one or more error intersections to obtain an updated set of one or more error intersections, wherein the Chase decoding is decoding upon combinatorically flipping certain least reliable bits;

a bit location selector configured to:

select, from the set of one or more error intersections, a set of one or more least reliable bit locations using soft information associated with the set of error-containing codewords; and

a decoder configured to:

perform the Chase decoding on the set of error-containing codewords based on a first value being a number of least reliable bit locations and a second value being a maximum number of allowable flips allowed out of the number of least reliable bit locations.

14. The memory device of claim 13 , wherein a number of erroneous bits in the set of least reliable bit locations is less than a correction capability of the memory device plus the second value.

15. The memory device of claim 14 , wherein the number of erroneous bits is at least equal to the second value.

16. The memory device of claim 13 , wherein the Chase decoder performs the Chase decoding in at least an initial iteration and a subsequent iteration.

17. The memory device of claim 16 , wherein the first value is increased at the subsequent iteration.

18. The memory device of claim 16 , wherein the second value is decreased at the subsequent iteration.