Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.
1. A substrate structure for use in a semiconductor device, comprising:
an array of copper pillar structures extending over one or more lines of a first direction and/or one or more lines of a second direction on top of a substrate layer;
wherein the copper pillar structures have a substantially cylindrical shape with a width of from 1 μm to 3 μm and a height of from 2 μm to 9 μm and an aspect height/width ratio of from 2 to 3;
wherein the copper pillar structures are separated in the first direction and/or the second direction by a pitch, defined from a center of a first pillar structure to a center of a second pillar structure, of from 4 μm to 5 μm; and
wherein each copper pillar structure has an oxide layer or a nitride layer on its surface and in contact with its base.
2. The substrate structure of claim 1 , wherein the base comprises a first TiW, Ti or TiN layer with a thickness of about 30 nm and a second Cu seed layer with a thickness of about 100 nm.
3. The substrate structure of claim 1 , wherein the oxide layer or the nitride layer on a surface of the substrate layer has a thickness of from 100 nm to 300 nm.
4. The substrate structure of claim 1 , wherein each copper pillar structure comprises an undercut region at the base which is smaller than 100 nm.
5. The substrate structure of claim 1 , wherein each base has a form of an extended base which is wider than a top part of the pillar.
6. The substrate structure of claim 1 , wherein a difference in height between the copper pillar structures of the array is less than 0.5 μm.
7. The substrate structure of claim 1 , wherein each copper pillar structure further comprises a solder material layer and a barrier material layer, wherein the barrier material layer is situated between the solder material layer and a copper pillar of the copper pillar structure, thereby forming an array of micro bump structures.
8. The substrate structure of claim 7 , wherein the solder material layer comprises at least 85% Sn or In, and the barrier material layer is Ni, Co, or Pd.
9. The substrate structure of claim 7 , wherein the micro bump structures have a substantially cylindrical or cylindrical-like shape with a width of from 1 μm to 3 μm and a height of from 2 μm to 9 μm and an aspect height/width ratio of from 2 to 3.
10. The substrate structure of claim 7 , wherein the copper pillar structures have a height of from 1.5 μm to 7 μm, wherein the barrier material layer has a height of 0.5 μm, and wherein the solder material layer has a height of from 1.5 μm to 7 μm.
11. The substrate structure of claim 1 , which is a component of an integrated circuit, a semiconductor wafer or an electronic device.
12. The substrate structure of claim 1 , wherein the copper pillar structures comprise a copper plate.
13. The substrate structure of claim 1 , wherein the copper pillar structures are electroplated.