Circuit for generating a reference current proportional to square of clock frequency

1. An analog-to-digital conversion system, comprising:

a plurality of integrators coupled to each other, each of said integrators requiring a reference current; and

a reference current generation circuit that generates said reference current for the plurality of integrators, the reference current is proportional to a square of a frequency of a clock signal of the reference current generation circuit.

2. The system of claim 1 , wherein the reference current generation circuit comprises at least two equally-sized MOSFETs of the same type and a switched-capacitor resistor including two equally-sized capacitors, and wherein at least one of said MOSFETs produces the reference current.

3. The system of claim 1 , wherein the reference current generation circuit comprises a switched-capacitor resistor that includes a plurality of switches and multiple capacitors, each of said switches controlled by said clock signal or by another clock signal.

4. The system of claim 3 , wherein the clock signals have a phase offset of 180 degrees.

5. The system of claim 4 , wherein said plurality of switches includes a first pair of switches that couple to a MOSFET in the reference current generation circuit, and the plurality of switches further includes a second pair of switches that couple to ground, and wherein each of the switches in the first pair is controlled by a different one of said clock signals, and wherein each of the switches in the second pair is controlled by a different one of said clock signals.

6. The system of claim 3 , wherein the reference current generation circuit comprises another capacitor coupled in parallel to the switched-capacitor resistor.

7. The system of claim 1 , wherein the reference current equals:

8

μ

N

⁡

(

Cox

)

⁢

(

W

L

)

MN

⁢

⁢

1

⁢

(

1

-

1

√

K

)

2

⁢

(

C

2

⁢

f

2

)

wherein μ is electron mobility for a MOSFET in the reference current generation circuit, Cox is gate oxide film capacitance per unit area for said MOSFET, W/L is an aspect ratio for said MOSFET, K is a size ratio of said MOSFET to another MOSFET in the reference current generation circuit, C is a capacitance of equally-sized multiple capacitors in a switched-capacitor resistor within the reference current generation circuit, and f is the frequency of the clock signal.

8. A reference current generation circuit for a delta-sigma analog-to-digital converter, comprising: a switched-capacitor resistor having multiple switches controlled by a clock signal and including multiple capacitors coupled to at least some of said switches;

a first MOSFET coupled to the switched-capacitor resistor and to a different capacitor;

a second MOSFET coupled to the first MOSFET and further coupled to said different capacitor, said first and second MOSFETS of the same type;

a third MOSFET coupled to the first MOSFET, to a fourth MOSFET, and to said different capacitor, said fourth MOSFET coupled to the second MOSFET and being of the same type as the third MOSFET; and

a fifth MOSFET of the same type as the third and fourth MOSFETs, coupled to the third MOSFET and producing a reference current, wherein the reference current is proportional to a square of a frequency of the clock signal.

9. The circuit of claim 8 , further comprising another capacitor coupled to the first MOSFET and to a node at which two of the multiple switches couple to each other, such that said another capacitor is in parallel with the switched-capacitor resistor.

10. The circuit of claim 8 , wherein the fifth MOSFET is coupled to a current mirror that mirrors said reference current.

11. The circuit of claim 8 , wherein each of the multiple switches is controlled by said clock signal or by a different clock signal, and wherein the clock signals have the same frequency.

12. The circuit of claim 11 , wherein the phases of the clock signals are offset by 180 degrees.

13. The circuit of claim 8 , wherein the third and fourth MOSFETs are equally sized.

14. The circuit of claim 8 , wherein said multiple capacitors in the switched-capacitor resistor are equally sized.

15. The circuit of claim 8 , wherein the reference current equals:

8

μ

N

⁡

(

Cox

)

⁢

(

W

L

)

MN

⁢

⁢

1

⁢

(

1

-

1

√

K

)

2

⁢

(

C

2

⁢

f

2

)

wherein μ is electron mobility for the second MOSFET, Cox is gate oxide film capacitance per unit area for the second MOSFET, W/L is an aspect ratio for the second MOSFET, K is a size ratio of the first MOSFET to the second MOSFET, C is a capacitance of the equally-sized multiple capacitors in the switched-capacitor resistor, and f is the frequency of the clock signal.

16. The circuit of claim 8 , further comprising a low-pass filter positioned between the third and fifth MOSFETs.

17. The circuit of claim 16 , wherein the low-pass filter comprises a plurality of resistors and a plurality of capacitors, each of said capacitors coupled between a different pair of said resistors.

18. The circuit of claim 8 , wherein the fifth MOSFET couples to a sixth MOSFET, said sixth MOSFET emits a constant current that combines with the reference current to produce a modified reference current.

19. The circuit of claim 18 , wherein the constant current is produced independent of the frequency of the clock signal.

20. The circuit of claim 8 , wherein the second and fourth MOSFETs couple to a startup circuit, and wherein the startup circuit comprises:

a first p-type MOSFET coupled to a second p-type MOSFET;

a capacitor coupled to the second p-type MOSFET;

a third p-type MOSFET coupled to the capacitor;

a first n-type MOSFET coupled to the third p-type MOSFET and coupled to the first p-type MOSFET; and

a second n-type MOSFET coupled to the second p-type MOSFET and coupled to the first n-type MOSFET.