Pixel and circuit design for image sensors with hole-based photodiodes
In order to reduce dark current and pixel readout noise in an image sensor, pixels may include a p-type hole-based pinned photodiode. Charge stored in the p-type pinned photodiode may be transferred to a p-type floating diffusion (FD) node and read out by pixel circuitry that uses p-channel metal oxide-semiconductor field-effect transistors (p-channel MOSFET). Additionally, the pixel circuitry may be split across multiple wafers that are connected by metal interconnect layers. This arrangement may enable the pixel photodiode to have a larger size than if all of the pixel circuitry was in a single wafer.
1. An imaging pixel array comprising:
a first substrate layer;
a second substrate layer;
a p-type photodiode formed in the first substrate layer;
a source follower transistor, wherein the source follower transistor is a p-channel metal-oxide-semiconductor field-effect transistor;
an interconnect layer that couples the first substrate layer to the second substrate layer;
a floating diffusion region formed in the first substrate layer, wherein the floating diffusion region comprises a lightly doped p-type floating diffusion region; and
a third substrate layer, wherein the third substrate layer includes one or more circuits selected from the group consisting of: a clock generating circuit, a pixel addressing circuit, a signal processing circuit, an analog to digital converter circuit, a digital image processing circuit, and a system interface circuit.
2. The imaging pixel array defined in claim 1 , further comprising:
an additional interconnect layer that couples the second substrate layer to the third substrate layer.
3. An imaging pixel array comprising:
a first substrate layer;
a second substrate layer;
a p-type photodiode formed in the first substrate layer;
a source follower transistor, wherein the source follower transistor is a p-channel metal-oxide-semiconductor field-effect transistor;
an interconnect layer that couples the first substrate layer to the second substrate layer; and
a passivation layer formed on the back side of the first substrate layer, wherein the passivation layer comprises a passivation layer selected from the group consisting of: n-type implants in the first substrate layer and a positively charged thin film.
4. The imaging pixel array defined in claim 3 , wherein the passivation layer comprises the n-type implants in the first substrate layer.
5. The imaging pixel array defined in claim 3 , wherein the passivation layer comprises the positively charged thin film.
6. The imaging pixel array defined in claim 3 , further comprising a color filter layer and an anti-reflection coating, wherein the anti-reflection coating is interposed between the passivation layer and the color filter layer.
7. The imaging pixel array defined in claim 1 , further comprising:
a transfer transistor formed in the first substrate layer.
8. The imaging pixel array defined in claim 7 , further comprising:
a reset transistor formed in the second substrate layer, wherein the reset transistor is a p-channel metal-oxide-semiconductor field-effect transistor.
9. The imaging pixel array defined in claim 8 , further comprising:
a row select transistor formed in the second substrate layer, wherein the row select transistor is a p-channel metal-oxide-semiconductor field-effect transistor.
10. The imaging pixel array defined in claim 1 , wherein the interconnect layer comprises metal.
11. The imaging pixel array defined in claim 10 , further comprising:
an additional floating diffusion region formed in the second substrate layer, wherein the additional floating diffusion region comprises a lightly doped p-type floating diffusion region.
12. The imaging pixel array defined in claim 11 , wherein the interconnect layer is interposed between the floating diffusion region and the additional floating diffusion region.
13. The imaging pixel array defined in claim 1 , further comprising:
an n-type doped pinning layer adjacent to the p-type photodiode.
14. The imaging pixel array defined in claim 1 , wherein the source follower transistor is formed in the second substrate layer.