SEMICONDUCTOR PACKAGE WITH INTERPOSER
Implementations of semiconductor packages may include: a first semiconductor die coupled to a first side of a substrate having one or more internal traces. One or more connectors coupled to the first semiconductor die and the first side of the substrate. A glass lid coupled to the first side of the substrate over the first semiconductor die. A mold compound that encapsulates at least a portion of the substrate. A second semiconductor die coupled to a second side of the substrate opposing the first side. The second semiconductor die is electrically coupled with the first semiconductor die through the one or more traces of the substrate.
1 . A semiconductor package comprising:
a first semiconductor die coupled to a first side of a substrate comprising one or more internal traces;
one or more connectors coupled to the first semiconductor die and the first side of the substrate;
a glass lid coupled to the first side of the substrate over the first semiconductor die;
a mold compound that encapsulates at least a portion of the substrate; and
a second semiconductor die coupled to a second side of the substrate opposing the first side;
wherein the second semiconductor die is electrically coupled with the first semiconductor die through the one or more traces of the substrate.
2 . The semiconductor package of claim 1 , further comprising at least one of a ball grid array, a land grid array, a pin grid array and any combination thereof coupled to the second side of the substrate.
3 . The semiconductor package of claim 1 , wherein the one or more connectors are wire bonds.
4 . The semiconductor package of claim 1 , wherein the substrate is coupled to a motherboard using wire bonds.
5 . (canceled)
6 . The semiconductor package of claim 1 , wherein the substrate is selected from the group consisting of a ceramic, an organic and any combination thereof.
7 . A semiconductor package comprising:
a first imaging chip coupled to a first side of an interposer comprising one or more internal traces;
one or more connectors coupled to the first imaging chip and the first side of the interposer;
a glass lid coupled to the first side of the interposer over the first imaging chip;
a mold compound that encapsulates at least a portion of the substrate;
a ball grid array coupled to a second side of the interposer; and
a second imaging chip coupled to the second side of the interposer;
wherein the second imaging chip is electrically coupled to the first imaging chip through the one or more traces of the interposer.
8 . The semiconductor package of claim 7 , wherein the one or more connectors are wire bonds.
9 . The semiconductor package of claim 7 , wherein the interposer is coupled to a motherboard using wire bonds.
10 . (canceled)
11 . The semiconductor package of claim 7 , wherein the substrate is selected from the group consisting of a ceramic, an organic and any combination thereof.
12 - 20 . (canceled)