Instruction provider and method for providing a sequence of instructions, test processor and method for providing a device under test

1. An apparatus comprising:

an instruction provider configured to provide a sequence of instructions based on a representation of a sequence of test vectors, each instruction defining provision of at least one test vector to a device under test;

wherein the instruction provider is configured to identify in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors, to store the identified subsequences of test vectors in a dictionary memory structure as indexed entries, and to provide the sequence of instructions comprising a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure, and a second instruction defining a second provision of the first subsequence of test vectors; and

wherein the first instruction and the second instruction reference a same indexed entry of the dictionary memory structure;

wherein the instruction provider is configured to provide the sequence of instructions further comprising a third instruction defining a third provision of a true subset of the first subsequence of test vectors; and

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors.

2. The apparatus according to claim 1 ,

wherein a first entry comprises the first subsequence of test vectors.

3. The apparatus according to claim 1 ,

wherein each test vector defines provision of a plurality of signal states and/or signal transitions in a device under test signal which is to be provided to the device under test.

4. The apparatus according to claim 1 ,

wherein the instruction provider is configured to further store a second subsequence of test vectors in the dictionary memory structure, wherein a length of the first subsequence of test vectors is different from a length of the second subsequence of test vectors.

5. The apparatus according to claim 1 ,

wherein the instruction provider is configured to compare a newly identified subsequence of test vectors with subsequences of test vectors already stored in the dictionary memory structure; and

wherein the instruction provider is configured to, if the newly identified subsequence of test vectors is a true subset of an already stored subsequence of test vectors, omit storing the newly identified subsequence of test vectors and provide in the sequence of instructions an instruction defining a provision of the newly identified subsequence of test vectors as a true subset of the already stored subsequence of test vectors.

6. The apparatus according to claim 1 ,

wherein the instruction provider is configured to compare a newly identified subsequence of test vectors with the subsequences of test vectors already stored in the dictionary memory structure; and

wherein the instruction provider is configured to, if an already stored subsequence of test vectors is a true subset of a newly identified subsequence of test vectors, remove the already stored subsequence of test vectors from the dictionary memory structure, store the newly identified subsequence of test vectors in the dictionary memory structure, and replace instructions in the sequence of instructions referencing to the removed subsequence of test vectors in the dictionary memory structure with instructions referencing to the newly identified subsequence of test vectors in the dictionary memory structure and defining the provision of the removed subsequence of test vectors as a true subset of the newly identified subsequence of test vectors.

7. The apparatus according to claim 1 ,

wherein the representation of the sequence of test vectors is a stream of test vectors; and

wherein the instruction provider is configured to receive the stream of test vectors and to provide based on the stream of test vectors the sequence of instructions.

8. An apparatus comprising:

a test processor configured to provide a device under test signal for a device under test based on a sequence of instructions;

wherein the test processor is configured to acquire an entry of a dictionary memory structure in response to a first instruction in the sequence of instructions, wherein the entry represents a first subsequence of test vectors stored in the dictionary memory structure;

wherein the test processor is configured to acquire another entry of the dictionary memory structure in response to a second instruction in the sequence of instructions, wherein the another entry represents the first subsequence of test vectors stored in the dictionary memory structure;

wherein the test processor is configured to acquire an additional entry of the dictionary memory structure in response to a third instruction in the sequence of instructions, wherein the additional entry represents the first subsequence of test vectors stored in the dictionary memory structure, and wherein the third instruction defines a provision of a true subset of the first subsequence of test vectors;

wherein the first instruction and the second instruction reference a same entry of the dictionary memory structure;

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors; and

wherein the test processor is configured to provide the device under test signal based on subsequences of test vectors from the entry, the another entry, and the additional entry.

9. The apparatus according to claim 8 ,

wherein the test processor is configured to choose the true subset of test vectors out of the subsequence of test vectors in dependence on a current instruction; and

wherein the test processor is further configured to provide the device under test signal based on the chosen true subset.

10. The apparatus according to claim 8 , wherein each test vector defines a set of signal states and/or signal transitions of the device under test signal.

11. The apparatus according to claim 8 , further comprising:

a memory comprising the dictionary memory structure.

12. A method for providing a sequence of instructions based on a representation of a sequence of test vectors, each instruction defining provision of at least one test vector to a device under test, the method comprising:

identifying in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors;

storing the identified subsequences of test vectors in a dictionary memory structure as indexed entries; and

providing the sequence of instructions comprising a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and a second instruction defining a second provision of the first subsequence of test vectors;

wherein the first instruction and the second instruction reference a same indexed entry of the dictionary memory structure;

wherein the sequence of instructions further comprises a third instruction defining a third provision of a true subset of the first subsequence of test vectors; and

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors.

13. A method for providing a device under test signal for a device under test based on a sequence of instructions, the method comprising:

acquiring an entry of a dictionary memory structure in response to a first instruction in the sequence of instructions, wherein the entry represents a first subsequence of test vectors stored in the dictionary memory structure;

acquiring another entry of the dictionary memory structure in response to a second instruction in the sequence of instructions, wherein the another entry represents the first subsequence of test vectors stored in the dictionary memory structure;

acquiring an additional entry of the dictionary memory structure in response to a third instruction in the sequence of instructions, wherein the additional entry represents the first subsequence of test vectors stored in the dictionary memory structure, and wherein the third instruction defines a provision of a true subset of the first subsequence of test vectors;

wherein the first instruction and the second instruction reference a same entry of the dictionary memory structure;

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors; and

providing the device under test signal based on subsequences of test vectors from the entry, the another entry, and the additional entry.

14. A non-transitory digital storage medium having a computer program stored thereon to perform a method for providing a sequence of instructions based on a representation of a sequence of test vectors, each instruction defining provision of at least one test vector to a device under test, the method comprising:

identifying in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors;

storing the identified subsequences of test vectors in a dictionary memory structure as indexed entries; and

providing the sequence of instructions comprising a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and a second instruction defining a second provision of the first subsequence of test vectors;

wherein the first instruction and the second instruction reference a same indexed entry of the dictionary memory structure;

wherein the sequence of instructions further comprises a third instruction defining a third provision of a true subset of the first subsequence of test vectors; and

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors,

wherein said computer program is run by a computer.

15. A non-transitory digital storage medium having a computer program stored thereon to perform a method for providing a device under test signal for a device under test based on a sequence of instructions, the method comprising:

acquiring an entry of a dictionary memory structure in response to a first instruction in the sequence of instructions, wherein the entry represents a first subsequence of test vectors stored in the dictionary memory structure;

acquiring another entry of the dictionary memory structure in response to a second instruction in the sequence of instructions, wherein the another entry represents the first subsequence of test vectors stored in the dictionary memory structure;

acquiring an additional entry of the dictionary memory structure in response to a third instruction in the sequence of instructions, wherein the additional entry represents the first subsequence of test vectors stored in the dictionary memory structure, and wherein the third instruction defines a provision of a true subset of the first subsequence of test vectors;

wherein the first instruction and the second instruction reference to a same entry of the dictionary memory structure;

wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors; and

providing the device under test signal based on subsequences of test vectors from the entry, the another entry, and the additional entry,

wherein said computer program is run by a computer.