IP Library Granted Patent US 9,779,989
Granted Patent B1
US 9,779,989 · App. 15/168,095 · Granted Oct 3, 2017

Method for manufacturing metal interconnects

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,779,989
App. No.
15/168,095
Granted
Oct 3, 2017
Kind
B1
Abstract

A method for manufacturing metal interconnects. The method includes following steps. A substrate including a dielectric layer formed thereon is provided, and a plurality of trenches are formed in the dielectric layer. Next, a seed layer is formed in the trenches and on the dielectric layer and followed by masking regions of the seed layer to define a plurality of masked regions and a plurality of exposed regions for the seed layer. Subsequently, a surface treatment is performed to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer. Then, a metal layer is formed on the substrate, and the trenches are filled up with the metal layer.

Claims (30)

1. A method for manufacturing metal interconnects, comprising:

providing a substrate comprising a dielectric layer formed thereon, and a plurality of trenches being formed in the dielectric layer;

forming a seed layer in the trenches and on the dielectric layer;

masking regions of the seed layer to define a plurality of masked regions correspondingly to the trenches and a plurality of exposed regions for the seed layer;

performing a surface treatment to the exposed regions of the seed layer to form a plurality of rough surfaces on the exposed regions of the seed layer; and

forming a metal layer on the substrate, and the trenches being filled up with the metal layer.

2. The method for manufacturing the metal interconnects according to claim 1 , further comprising forming a sacrificial layer respectively in the trenches before masking the regions of the seed layer.

3. The method for manufacturing the metal interconnects according to claim 2 , wherein the surface treatment comprises an ion bombardment.

4. The method for manufacturing the metal interconnects according to claim 3 , wherein the ion bombardment comprises producing nitrogen (N), boron (B), arsenic (As), phosphorous (P), inert, or halogen ions.

5. The method for manufacturing the metal interconnects according to claim 4 , wherein the ion bombardment comprises providing halogen ions with lower bias.

6. The method for manufacturing the metal interconnects according to claim 1 , wherein the surface treatment comprises exposure.

7. The method for manufacturing the metal interconnects according to claim 6 , wherein the exposure comprises Laser or UV.

8. The method for manufacturing the metal interconnects according to claim 1 , further comprising at least a via hole formed under one of the plurality of trenches.

9. The method for manufacturing the metal interconnects according to claim 1 , further comprising a diffusion barrier layer formed under the seed layer.

10. The method for manufacturing the metal interconnects according to claim 1 , further comprising performing a planarization process to remove superfluous metal layer from the substrate to form a plurality of metal interconnects on the substrate.

11. A method for manufacturing metal interconnects, comprising:

providing a substrate comprising a dielectric layer formed thereon, and a plurality of trenches being formed in the dielectric layer;

masking the trenches to define a plurality of exposed regions on the dielectric layer;

performing a surface treatment to the exposed regions to form a plurality of rough surfaces on the exposed regions;

forming a seed layer on the substrate after the surface treatment, the seed layer comprising a plurality of rough surfaces respectively on the exposed regions; and

forming a metal layer on the substrate, and the trenches being filled up with the metal layer.

12. The method for manufacturing the metal interconnects according to claim 11 , further comprising forming a sacrificial layer respectively in the trenches before masking the trenches.

13. The method for manufacturing the metal interconnects according to claim 12 , wherein the surface treatment comprises an ion bombardment.

14. The method for manufacturing the metal interconnects according to claim 13 , wherein the ion bombardment comprises producing N, B, As, P, inert, or halogen ions.

15. The method for manufacturing the metal interconnects according to claim 14 , wherein the ion bombardment comprises providing halogen ions with lower energy.

16. The method for manufacturing the metal interconnects according to claim 11 , wherein the surface treatment comprises exposure to Laser or UV.

17. The method for manufacturing the metal interconnects according to claim 11 , further comprising at least a via hole formed under one of the plurality of trenches.

18. The method for manufacturing the metal interconnects according to claim 11 , further comprising a diffusion barrier layer formed under the seed layer.

19. The method for manufacturing the metal interconnects according to claim 18 , wherein the diffusion barrier layer comprises the rough surfaces.

20. The method for manufacturing the metal interconnects according to claim 11 , further comprising performing a planarization process to remove superfluous metal layer from the substrate to form a plurality of metal interconnects on the substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2016
From: HUANG, PO-CHENG; LIU, CHUN-LIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 038978/0643 →