Image sensor semiconductor packages and related methods
An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
1. An image sensor semiconductor package, comprising:
a printed circuit board (PCB) comprising a first surface and a second surface opposite the first surface;
an interposer comprising a first surface and a second surface opposite the first surface of the interposer, the interposer comprising a recess in its second surface and comprising one or more electrical vias passing through the interposer from the first surface of the interposer to the second surface of the interposer;
a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die comprising a first surface comprising a photosensitive region and a second surface opposite the first surface of the CIS die, the second surface of the CIS die directly coupled with the first surface of the interposer;
an image signal processor (ISP) coupled within the recess of the interposer;
one or more electrical couplers electrically coupling the CIS die with the PCB through the one or more electrical vias of the interposer;
one or more redistribution layers (RDLs) fanning out one or more electrical contacts of the ISP by electrically coupling the one or more electrical contacts of the ISP with one or more of a plurality of electrical contacts comprised at the second surface of the PCB, and;
the plurality of electrical contacts comprised at the second surface of the PCB and electrically coupled with the CIS die and with the ISP;
wherein the recess comprised in the interposer does not extend to the first surface of the interposer; and
wherein the second surface of the interposer is coupled to the first surface of the PCB.
2. The package of claim 1 , wherein the package does not comprise an image signal processor at the second surface of the PCB.
3. A method of forming an image sensor semiconductor package, comprising:
providing an interposer comprising a first surface and a second surface opposite the first surface of the interposer, the second surface of the interposer comprising a recess therein;
forming one or more electrical vias through the interposer from the first surface of the interposer to the second surface of the interposer;
coupling an image signal processor (ISP) within the recess of the interposer and electrically coupling the ISP with the one or more electrical vias;
coupling the interposer with a first surface of a printed circuit board (PCB), the PCB also having a second surface opposite the first surface of the PCB;
coupling a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die with the interposer, the CIS die comprising a first surface comprising a photosensitive region and a second surface opposite the first surface of the CIS die, the second surface of the CIS die directly coupled with the first surface of the interposer;
electrically coupling the CIS die with one or more electrical contacts located at the second surface of the PCB through the one or more electrical vias of the interposer;
electrically coupling the ISP with the CIS die through the one or more electrical vias of the interposer; and
forming one or more redistribution layers (RDLs) electrically coupling one or more electrical contacts of the ISP with one or more of the plurality of electrical contacts comprised at the second surface of the PCB;
wherein the recess comprised in the interposer does not extend to the first surface of the interposer.
4. The method of claim 3 , further comprising at least partially encapsulating the CIS die in an encapsulant.