IP Library › Granted Patent US 10,249,606
Granted Patent B2
US 10,249,606 · App. 15/169,002 · Granted Apr 2, 2019

Semiconductor device

Inventor: Teruo Suzuki (Komono, JP)
Assignee: SOCIONEXT INC.
H01L27/0255H01L27/027
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Quick Facts
Patent No.
US 10,249,606
App. No.
15/169,002
Granted
Apr 2, 2019
Kind
B2
Abstract

A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

Claims (47)

1. A semiconductor device comprising:

a first domain that includes a first high power source line, a first low power source line, and a first power clamp circuit provided between the first high power source line and the first low power source line;

a second domain that include a second high power source line separated from the first high power source line, a second low power source line separated from the first low power source line, and a second power clamp circuit provided between the second high power source line and the second low power source line;

a third power clamp circuit provided between the second high power source line and the first low power source line;

a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and

a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein

the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line,

wherein

the first relay circuit is a level shifter,

the first relay circuit includes a first complementary signal generation circuit that is connected to the first high power source line and the first low power source line, and that generates a complementary signal of a signal from the first domain, and

the first relay circuit includes a first differential circuit that is connected to the second high power source line and the first low power source line, that receives a complementary signal from the first complementary signal generation circuit, and that outputs a first output to the second domain.

2. The semiconductor device according to claim 1 , wherein

the first low power source line and the second low power source line are separated via a bidirectional diode.

3. The semiconductor device according to claim 1 , wherein

a voltage between the first high power source line and the first low power source line is set to a voltage lower than or equal to a voltage between the second high power source line and the second low power source line.

4. The semiconductor device according to claim 2 , wherein

the second relay circuit is a level shifter.

5. The semiconductor device according to claim 4 , wherein the second relay circuit includes:

a second complementary signal generation circuit that is connected to the second high power source line and the first low power source line, and that generates a complementary signal of a signal from the second domain; and

a second differential circuit that is connected to the first high power source line and the first low power source line, that receives a complementary signal from the second complementary signal generation circuit, and that outputs a second output to the first domain.

6. The semiconductor device according to claim 2 , wherein

a voltage between the first high power source line and the first low power source line is set to a voltage lower than or equal to a voltage between the second high power source line and the second low power source line.

7. The semiconductor device according to claim 3 , wherein

the second relay circuit is a level shifter.

8. The semiconductor device according to claim 1 , wherein

the second relay circuit is a level shifter.

9. The semiconductor device according to claim 7 , wherein the second relay circuit include:

a second complementary signal generation circuit that is connected to the second high power source line and the first low power source line, and that generates a complementary signal of a signal from the second domain; and

a second differential circuit that is connected to the first high power source line and the first low power source line, that receives a complementary signal from the second complementary signal generation circuit, and that outputs a second output to the first domain.

10. The semiconductor device according to claim 8 , wherein the second relay circuit includes:

a second complementary signal generation circuit that is connected to the second high power source line and the first low power source line, and that generates a complementary signal of a signal from the second domain; and

a second differential circuit that is connected to the first high power source line and the first low power source line, that receives a complementary signal from the second complementary signal generation circuit, and that outputs a second output to the first domain.

11. A semiconductor device comprising:

a first domain that includes a first high power source line, a first low power source line, and a first power clamp circuit provided between the first high power source line and the first low power source line;

a second domain that include a second high power source line separated from the first high power source line, a second low power source line separated from the first low power source line, and a second power clamp circuit provided between the second high power source line and the second low power source line;

a third power clamp circuit provided between the second high power source line and the first low power source line;

a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and

a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein

the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line,

wherein

the second relay circuit is a level shifter,

the second relay circuit includes a second complementary signal generation circuit that is connected to the second high power source line and the first low power source line, and that generates a complementary signal of a signal from the second domain, and

the second relay circuit includes a differential circuit that is connected to the first high power source line and the first low power source line, that receives a complementary signal from the second complementary signal generation circuit, and that outputs an output to the first domain.

12. The semiconductor device according to claim 11 , wherein

the first low power source line and the second low power source line are separated via a bidirectional diode.

13. The semiconductor device according to claim 11 , wherein

a voltage between the first high power source line and the first low power source line is set to a voltage lower than or equal to a voltage between the second high power source line and the second low power source line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2016
From: SUZUKI, TERUO
To: SOCIONEXT INC.
Reel/Frame 038851/0854 →
Priority Claims (1)
JP 2015-123990 · Jun 19, 2015 · national
Continuity (1)
Related Publication 20160372453A1 · Dec 22, 2016
Cited By (1)
US 12,607,666