SRAM cell and logic cell design
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
1. A semiconductor device comprising:
a first static random access memory (SRAM) array comprising a plurality of SRAM cells, each of the plurality of SRAM cells having a first cell height; and
a first logic cell outside of the first SRAM array, the first logic cell having the first cell height.
2. The semiconductor device of claim 1 , wherein the first cell height is measured in a word line direction of the plurality of SRAM cells.
3. The semiconductor device of claim 1 , wherein the first logic cell comprises an inverter, a NAND gate, a NOR gate, a multiplexer, a latch, or a flip-flop.
4. The semiconductor device of claim 1 , wherein each of the plurality of SRAM cells comprises a first number of semiconductor fins, and wherein the first logic cell comprises the first number of semiconductor fins.
5. The semiconductor device of claim 4 , wherein each of the plurality of SRAM cells comprises a first elongated contact electrically connected to at least two of the first number of semiconductor fins, and wherein the first logic cell comprises a second elongated contact electrically connected to at least two of the first number of semiconductor fins.
6. The semiconductor device of claim 1 , wherein each of the plurality of SRAM cells comprises:
a first pair of cross-connected inverters providing two storage data nodes;
a first pass-gate transistor electrically connected to the first pair of cross-connected inverters; and
a second pass-gate transistor electrically connected to the first pair of cross-connected inverters, wherein gates of the first pass-gate transistor and the second pass-gate transistor are electrically connected to a word line.
7. The semiconductor device of claim 6 , wherein the first pair of cross-connected inverters comprises:
a first pull-up transistor and a second pull-up transistor; and
a first pull-down transistor and a second pull-down transistor forming cross-connected inverters with the first pull-up transistor and the second pull-up transistor.
8. The semiconductor device of claim 7 further comprising:
a first metal layer over the transistors, the first metal layer comprising a bit line and a first power supply line, sources of the first pull-up transistor and the second pull-up transistor are electrically connected to the first power supply line, the bit line and the first power supply line having longitudinal axes in a first direction, the word line having longitudinal axis in a second direction, the second direction being perpendicular to the first direction.
9. The semiconductor device of claim 8 , wherein the word line is in a second metal layer over the first metal layer.
10. The semiconductor device of claim 9 further comprising:
a third metal layer over the second metal layer, the third metal layer comprising a second and third power supply lines, sources of the first pull-down transistor and the second pull-down transistor are electrically connected to the second and third power supply lines, respectively, the second and third power supply lines having longitudinal axes in the second direction.
11. An integrated circuit structure comprising:
a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary; and
a logic cell having the first number of semiconductor fins and the first cell height.
12. The integrated circuit structure of claim 11 , wherein the logic cell comprises an inverter, a NAND gate, a NOR gate, a multiplexer, a latch, or a flip-flop.
13. The integrated circuit structure of claim 11 , wherein the SRAM cell further comprises:
a first pull-up metal-oxide-semiconductor (MOS) device and a second pull-up MOS device; and
a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device;
a first pass-gate MOS device having a source/drain electrically connected to drains of the first pull-up MOS device and the first pull-down MOS device; and
a second pass-gate MOS device having a source/drain electrically connected to drains of the second pull-up MOS device and the second pull-down MOS device, wherein gates of the first pass-gate MOS device and the second pass-gate MOS device are electrically connected to a word line.
14. The integrated circuit structure of claim 13 , wherein the word line is in a metal layer over the MOS devices, the word line extending from the third boundary to the fourth boundary.
15. The integrated circuit structure of claim 11 , wherein the logic cell comprises a p-type metal-oxide-semiconductor (PMOS) device and an n-type MOS (NMOS) device, the PMOS device being coupled between a first power supply line and a first node, the NMOS device being coupled between a second power supply line and the first node, the NMOS and PMOS devices sharing a common gate electrode.
16. The integrated circuit structure of claim 15 , wherein the PMOS device comprises three semiconductor fins extending over a substrate, wherein the NMOS device comprises three semiconductor fins extending over the substrate.
17. A semiconductor device comprising:
a first static random access memory (SRAM) array comprising a plurality of SRAM cells, each of the plurality of SRAM cells having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, each of the plurality of SRAM cells having a first cell height as measured from the third boundary to the fourth boundary; and
a first logic cell outside of the first SRAM array, the first logic cell comprising an inverter, a NAND gate, a NOR gate, a multiplexer, a latch, or a flip-flop, the first logic cell having the first cell height and the first number of semiconductor fins.
18. The semiconductor device of claim 17 , wherein each of the plurality of SRAM cells comprises a first elongated contact electrically connected to at least two of the first number of semiconductor fins, and wherein the first logic cell comprises a second elongated contact electrically connected to at least two of the first number of semiconductor fins.
19. The semiconductor device of claim 17 , wherein each of the plurality of SRAM cells further comprises:
a first pull-up metal-oxide-semiconductor (MOS) device and a second pull-up MOS device; and
a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device;
a first pass-gate MOS device having a source/drain electrically connected to drains of the first pull-up MOS device and the first pull-down MOS device; and
a second pass-gate MOS device having a source/drain electrically connected to drains of the second pull-up MOS device and the second pull-down MOS device, wherein gates of the first pass-gate MOS device and the second pass-gate MOS device are electrically connected to a word line.
20. The semiconductor device of claim 19 , wherein the word line is in a metal layer over the MOS devices, the word line extending from the third boundary to the fourth boundary.