IP Library Granted Patent US 10,448,518
Granted Patent B2
US 10,448,518 · App. 15/170,943 · Granted Oct 15, 2019

Method for manufacturing a circuit having a lamination layer using laser direct structuring process

Inventors: Seung Hyuk Choi (Gyeonggi-do, KR); Hyun Jun Hong (Gyeonggi-do, KR); Tae Wook Kim (Gyeonggi-do, KR); Cheong Ho Ryu (Gyeonggi-do, KR); Young Sang Kim (Gyeonggi-do, KR); Sung Jun Kim (Gyeonggi-do, KR)
Assignee: Ethertronics, Inc.
H05K3/4644H05K3/0014H05K3/0026H05K3/185H05K3/188H05K3/28H05K3/423H05K3/4652H05K2201/09118H05K2201/09827H05K2201/09854H05K2203/0582H05K2203/0588H05K2203/072H05K2203/107Y10T29/49124Y10T29/49155Y10T29/49165
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Quick Facts
Patent No.
US 10,448,518
App. No.
15/170,943
Granted
Oct 15, 2019
Kind
B2
Abstract

The present subject matter relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.

Claims (22)

1. A method for forming a multi-layer circuit structure, the method comprising:

forming a first circuit pattern on a substrate using a laser;

plating the first circuit pattern to form a first circuit on the substrate;

after plating the first circuit pattern, masking a connection region of the first circuit to form a masking;

after masking the connection region, applying a layer of paint over at least a portion of the first circuit;

after applying the layer of paint, removing the masking such that the connection region is not coated with the layer of paint;

forming a second circuit pattern on the layer of paint using the laser; and

plating the second circuit pattern to form a second circuit on the layer of paint.

2. The method of claim 1 , wherein the substrate comprises at least one curved surface and the first circuit is at least partially formed on the at least one curved surface.

3. The method of claim 1 , wherein plating the second circuit pattern comprises electrically connecting the second circuit with the first circuit at the connection region.

4. The method of claim 1 , wherein the first circuit pattern is formed on an upper surface of the substrate, and wherein the method further comprises forming a third circuit on a back surface of the substrate that is opposite the upper surface of the substrate.

5. The method of claim 4 , further comprising:

forming a through hole in the substrate; and

electrically connecting the first circuit with the third circuit at a location that is proximate the through hole.

6. The method of claim 5 , wherein a radius of the through hole is at least 1.5 times a total number of overlapping paint layers multiplied by a thickness of at least one of the first circuit or the second circuit.

7. The method of claim 5 , wherein forming the through hole comprises providing an angled surface on the substrate such that a diameter of the through hole increases from the back surface of the substrate to the upper surface of the substrate.

8. The method of claim 7 , wherein the angled surface of the substrate forms an angle with the upper surface of the substrate between 15 degrees and 30 degrees.

9. The method of claim 4 , wherein the substrate comprises an edge surface extending from the upper surface to the back surface, and wherein the method further comprises electrically connecting the first circuit with the third circuit along the edge surface of the substrate.

10. The method of claim 1 , wherein forming the second circuit pattern on the layer of paint using the laser comprises defining a pad area suitable for soldering a surface mount component to the second circuit.

11. The method of claim 1 , wherein the substrate comprises at least one of metal, glass, ceramic, or rubber.

12. The method of claim 1 , further comprising forming the substrate using injection molding.

13. The method of claim 1 , wherein plating the first circuit pattern or plating the second circuit pattern comprises forming a layer of conductive material having a thickness ranging from 25 μm to 50 μm.

Assignments (6)
CHANGE OF NAME Recorded May 4, 2023
From: AVX ANTENNA, INC.
To: KYOCERA AVX COMPONENTS (SAN DIEGO), INC.
Reel/Frame 063543/0302 →
CHANGE OF NAME Recorded May 2, 2023
From: ETHERTRONICS, INC.
To: AVX ANTENNA, INC.
Reel/Frame 063504/0692 →
RELEASE OF SECURITY INTEREST Recorded Jan 31, 2018
From: NH EXPANSION CREDIT FUND HOLDINGS LP
To: ETHERTRONICS, INC.
Reel/Frame 045210/0725 →
SECURITY INTEREST Recorded Aug 11, 2017
From: ETHERTRONICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 044106/0829 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2017
From: CHOI, SEUNG HYUK; HONG, HYUN JUN; KIM, TAE WOOK; RYU, CHEONG HO; KIM, YOUNG SANG; KIM, SUNG JUN
To: ETHERTRONICS, INC.
Reel/Frame 042089/0369 →
SECURITY INTEREST Recorded Oct 21, 2016
From: ETHERTRONICS, INC.
To: NH EXPANSION CREDIT FUND HOLDINGS LP
Reel/Frame 040464/0245 →
Priority Claims (1)
KR 10-2015-0078172 · Jun 2, 2015 · national
Continuity (1)
Related Publication 20170094801A1 · Mar 30, 2017