Power MOSFET with metal filled deep source contact

1. A method of fabricating a planar gate power metal-oxide-semiconductor field effect transistor (power MOSFET), comprising:

providing a planar gate power MOSFET die including a plurality of transistor cells (cells) including a first cell and at least a second cell formed on a substrate having a semiconductor surface doped a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface between said first and said second gate stack providing a source contact (SCT) from said substrate to a source doped a second conductivity type, a field plate (FP) over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal (PGM) metal filler (metal filler) within, and a drain doped said second conductivity type in said semiconductor surface on a side of said gate stacks opposite said trench, wherein said trench is formed by an etching process using self-alignment provided by said gate stacks;

first etching of said metal filler for removing said metal filler along a sidewall of said FP over said drain and removing a portion of said metal filler in said trench;

depositing said metal filler including to fill said trench, and

second etching of said metal filler.

2. The method of claim 1 , wherein said metal filler comprises tungsten (W).

3. The method of claim 1 , wherein said metal filler comprises Ta, Pt, or Pd.

4. The method of claim 1 , wherein said gate electrode comprises a metal silicide (WSi2) on polysilicon.

5. The method of claim 1 , wherein said substrate comprises a p+ substrate and said semiconductor surface comprises a p-epitaxial layer, and wherein said power MOSFET comprises NMOS.

6. The method of claim 1 , wherein said substrate comprises an n+ substrate and said semiconductor surface comprises an n-epitaxial layer, and wherein said power MOSFET comprises PMOS.

7. The method of claim 1 , wherein said first etching and said second etching both comprise plasma etching.

8. The method of claim 1 , wherein said FP comprises at least one refractory metal layer.

9. The method of claim 1 further comprising:

forming a substrate contact region at a bottom of said SCT after forming said trench, said substrate contact region being doped said first conductivity type.

10. The method of claim 1 , wherein said first etching further comprises increasing a distance from a boundary of the FP to a boundary of the drain.

11. The method of claim 1 , wherein said first etching further comprises reducing a probability of FP bridging the source to the drain.

12. A method of fabricating a planar gate power metal-oxide-semiconductor field effect transistor (power MOSFET), comprising:

providing a planar gate power MOSFET die including a plurality of transistor cells (cells) including a first cell and at least a second cell formed on a substrate having a semiconductor surface doped a first conductivity type, said first cell having a first gate stack and said second cell having a second gate stack, each said gate stack including a gate electrode on a gate dielectric over a body region, a trench having an aspect ratio of at least 3 extending down from a top side of said semiconductor surface between said first and said second gate stack providing a source contact (SCT) from said substrate to a source doped a second conductivity type, a field plate (FP) over said gate stacks extending to provide a liner for said trench, said trench having a refractory or platinum-group metal (PGM) metal filler (metal filler) within, and a drain doped said second conductivity type in said semiconductor surface on a side of said gate stacks opposite said trench, wherein said trench is formed by an etching process using self-alignment provided by said gate stacks;

first etching of said metal filler;

depositing said metal filler including to fill said trench, and

second etching of said metal filler.

13. The method of claim 12 , wherein said first etching of said metal filler removes said metal filler along a sidewall of said FP over said drain and removing a portion of said metal filler in said trench.

14. The method of claim 12 , wherein said metal filler comprises tungsten (W).

15. The method of claim 12 , wherein said metal filler comprises Ta, Pt, or Pd.

16. The method of claim 12 , wherein said gate electrode comprises a metal silicide (WSi2) on polysilicon.

17. The method of claim 12 , wherein said substrate comprises a p+ substrate and said semiconductor surface comprises a p-epitaxial layer, and wherein said power MOSFET comprises NMOS.

18. The method of claim 12 , wherein said substrate comprises an n+ substrate and said semiconductor surface comprises an n-epitaxial layer, and wherein said power MOSFET comprises PMOS.

19. The method of claim 12 , wherein said first etching and said second etching both comprise plasma etching.

20. The method of claim 12 , wherein said FP comprises at least one refractory metal layer.

21. The method of claim 12 further comprising:

forming a substrate contact region at a bottom of said SCT after forming said trench, said substrate contact region being doped with said first conductivity type.

22. The method of claim 12 , wherein said first etching comprises at least one of: increasing a distance from a boundary of the FP to a boundary of the drain and reducing a probability of FP bridging the source to the drain.