One-shot decoder for two-error-correcting BCH codes

1. A method of operating a memory system comprising:

receiving requests from a host device;

receiving a codeword and generating at least two syndromes based on the codeword;

generating an error-location polynomial based on the syndromes, wherein the generation of the error-location polynomial includes receiving the syndromes, generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, generating the error-location polynomial based on the combination of the coefficients, and finding at least one root of the error-location polynomial;

determining at least one error location based on the error-location polynomial, wherein the error location is based on a combination of the root and one of the syndromes; and

correcting the codeword based on the at least the one error location.

2. The method of claim 1 , wherein the generating the error-location polynomial includes:

squaring a first syndrome of the syndromes as a first coefficient to output a second coefficient;

multiplying the first coefficient by the second coefficient to output a multiplied result;

adding the multiplied result and a second syndrome of the syndromes to output a third coefficient; and

dividing the third coefficient by the multiplied result to output the combination of coefficients.

3. The method of claim 2 , wherein the generating the error-location polynomial includes:

dividing the second coefficient by the third coefficient.

4. The method of claim 3 , wherein the determining at least one error location includes:

multiplying the output of the additional divider by the root to output a first root;

adding the output of the additional divider and the first root to output a second root;

based on a first lookup table including a plurality of error locations corresponding to a plurality of roots, outputting a first error location value based on the first root; and

based on a second lookup table including a plurality of error locations corresponding to a plurality of roots, outputting a second error location value based on the second root.

5. The method of claim 2 , wherein the determining at least one error location includes:

multiplying a first syndrome of the syndromes by the root to output a first root;

adding the first syndrome and the first root to output a second root;

based on a first lookup table including a plurality of error locations corresponding to a plurality of roots, outputting a first error location value based on the first root; and

based on a second lookup table including a plurality of error locations corresponding to a plurality of roots, outputting a second error location value based on the second root.

6. The method of claim 2 , wherein the determining at least one error location includes:

multiplying a first syndrome of the syndromes by the root to output a first root;

adding the first syndrome and the first root to output a second root; and

based on a lookup table including a plurality of error locations corresponding to a plurality of roots, outputting an error location value based on one of the first root and the second root.

7. The method of claim 6 , further comprising:

receiving the first root and the second root and outputting one of the first root and the second root according to a selection signal to the lookup table.

8. The method of claim 7 , wherein the selection signal includes the third coefficient.

9. The method of claim 7 , further comprising:

receiving the first syndrome.

10. The method of claim 6 , further comprising:

outputting a first error location value based on the first root by a first flip-flop;

receiving the error location value from the lookup table and the output of the first flip-flop, and outputting to the first flip-flop one of the error location value and the output of the first flip-flop according to a selection signal as the first error location value;

outputting a second error location value based on the second root by a second flip-flop; and

a second multiplexer for receiving the error location value from the lookup table and the output of the second flip-flop, and outputting to the second flip-flop one of the error location value and the output of the second flip-flop according to the selection signal as the second error location value.

11. A memory system comprising

a host device configured to send requests;

a memory device including groups of memory cells, and configured to store data in accordance with the requests from the host device; and

a controller coupled with the host device and the memory device, and including a decoder configured to decode the data read from the memory device,

wherein the decoder comprises:

a syndrome generator receives a codeword of the data and generate at least two syndromes based on the codeword;

an error location polynomial generator generates an error-location polynomial based on the syndromes, wherein the error location polynomial generator includes:

a logic receives the syndromes and generates a combination of the syndromes as a combination of coefficients of the error-location polynomial; and

a key equation solver generates the error-location polynomial based on the combination of the coefficients and finds at least one root of the error-location polynomial;

an error location determiner determines at least one error location based on the error-location polynomial, wherein the error location determiner determines the error location based on at least a combination of the root and one of the syndromes; and

an error corrector corrects the codeword based on the at least one error location.

12. The memory system of claim 11 , wherein the logic includes:

a square operator for squaring a first syndrome of the syndromes as a first coefficient to output a second coefficient;

a multiplier for multiplying the first coefficient by the second coefficient to output a multiplied result;

an adder for adding the multiplied result and a second syndrome of the syndromes to output a third coefficient; and

a divider for dividing the third coefficient by the multiplied result to output the combination of coefficients.

13. The memory system of claim 12 , wherein the logic further includes:

an additional divider for dividing the second coefficient by the third coefficient.

14. The memory system of claim 13 , wherein the error location determiner includes:

a multiplier for multiplying the output of the additional divider by the root to output a first root;

an adder for adding the output of the additional divider and the first root to output a second root;

a first lookup table including a plurality of error locations corresponding to a plurality of roots, for outputting a first error location value based on the first root; and

a second lookup table including a plurality of error locations corresponding to a plurality of roots, for outputting a second error location value based on the second root.

15. The memory system of claim 12 , wherein the error location determiner includes:

a multiplier for multiplying a first syndrome of the syndromes by the root to output a first root;

an adder for adding the first syndrome and the first root to output a second root;

a first lookup table including a plurality of error locations corresponding to a plurality of roots, for outputting a first error location value based on the first root; and

a second lookup table including a plurality of error locations corresponding to a plurality of roots, for outputting a second error location value based on the second root.

16. The memory system of claim 12 , wherein the error location determiner includes:

a multiplier for multiplying a first syndrome of the syndromes by the root to output a first root;

an adder for adding the first syndrome and the first root to output a second root; and

a lookup table including a plurality of error locations corresponding to a plurality of roots, for outputting an error location value based on one of the first root and the second root.

17. The memory system of claim 16 , further comprising:

a multiplexer for receiving the first root and the second root, and outputting one of the first root and the second root according to a selection signal to the lookup table.

18. The memory system of claim 17 , wherein the selection signal includes the third coefficient.

19. The memory system of claim 17 , wherein the multiplexer further receives the first syndrome.

20. The memory system of claim 16 , further comprising:

a first flip-flop for outputting a first error location value based on the first root;

a first multiplexer for receiving the error location value from the lookup table and the output of the first flip-flop, and outputting to the first flip-flop one of the error location value and the output of the first flip-flop according to a selection signal as the first error location value;

a second flip-flop for outputting a second error location value based on the second root; and

a second multiplexer for receiving the error location value from the lookup table and the output of the second flip-flop, and outputting to the second flip-flop one of the error location value and the output of the second flip-flop according to the selection signal as the second error location value.