Manufacturing method of high-voltage metal-oxide-semiconductor transistor
A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.
1. A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device, comprising:
providing a semiconductor substrate;
forming a patterned conductive structure on the semiconductor substrate, wherein the patterned conductive structure comprises:
a gate structure, wherein the semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure; and
a first sub-gate structure disposed on the first region of the semiconductor substrate, wherein the first sub-gate structure is separated from the gate structure;
forming a drain region in the first region of the semiconductor substrate;
forming a first drift region in the semiconductor substrate, wherein the first drift region is at least partially formed in the first region of the semiconductor substrate, and the drain region is formed in the first drift region;
forming a first isolation structure in the first drift region, wherein at least a part of the first isolation structure is disposed between the drain region and the first sub-gate structure, and another part of the first isolation structure is disposed under the gate structure; and
forming a first contact structure on the drain region and the first sub-gate structure, wherein the drain region is electrically connected to the first sub-gate structure via the first contact structure.
2. The manufacturing method of claim 1 , further comprising:
forming a gate insulation layer on the semiconductor substrate before the step of forming the patterned conductive structure, wherein a first part of the gate insulation layer is disposed between the gate structure and the semiconductor substrate, and a second part of the gate insulation layer is disposed between the first sub-gate structure and the semiconductor substrate.
3. The manufacturing method of claim 2 , wherein a thickness of the first part is larger than a thickness of the second part.
4. The manufacturing method of claim 3 , wherein the second part of the gate insulation layer is partially etched for being thinner than the first part of the gate insulation layer.
5. The manufacturing method of claim 3 , wherein the thickness of the second part is larger than or equal to 5% of the thickness of the first part.
6. The manufacturing method of claim 1 , further comprising:
forming a second drift region in the semiconductor substrate, wherein the second drift region is at least partially formed in the second region of the semiconductor substrate; and
forming a source region in the second region of the semiconductor substrate, wherein the source region is formed in the second drift region.
7. The manufacturing method of claim 6 , wherein the patterned conductive structure further comprises a second sub-gate structure disposed on the second region of the semiconductor substrate, wherein the second sub-gate structure is separated from the gate structure and the first sub-gate structure, and the second sub-gate structure is electrically connected to the source region via a second contact structure formed on the second sub-gate structure and the source region.
8. The manufacturing method of claim 1 , further comprising:
forming a sidewall spacer layer on sidewalls of the gate structure and the first sub-gate structure, wherein a part of the sidewall spacer layer is disposed between the gate structure and the first sub-gate structure.
9. A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device, comprising:
providing a semiconductor substrate;
forming a patterned conductive structure on the semiconductor substrate, wherein the patterned conductive structure comprises:
a gate structure, wherein the semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure; and
a first sub-gate structure disposed on the first region of the semiconductor substrate, wherein the first sub-gate structure is separated from the gate structure;
forming a gate insulation layer on the semiconductor substrate before the step of forming the patterned conductive structure, wherein a first part of the gate insulation layer is disposed between the gate structure and the semiconductor substrate, and a second part of the gate insulation layer is disposed between the first sub-gate structure and the semiconductor substrate;
forming a drain region in the first region of the semiconductor substrate;
forming a first drift region in the semiconductor substrate, wherein the first drift region is at least partially formed in the first region of the semiconductor substrate, and the drain region is formed in the first drift region;
forming a first isolation structure in the first drift region, wherein at least a part of the first isolation structure is disposed between the drain region and the first sub-gate structure, and the second part of the gate insulation layer is disposed between the first sub-gate structure and the first isolation structure; and
forming a first contact structure on the drain region and the first sub-gate structure, wherein the drain region is electrically connected to the first sub-gate structure via the first contact structure.
10. The manufacturing method of claim 9 , wherein a thickness of the first part is larger than a thickness of the second part.
11. The manufacturing method of claim 10 , wherein the second part of the gate insulation layer is partially etched for being thinner than the first part of the gate insulation layer.
12. The manufacturing method of claim 10 , wherein the thickness of the second part is larger than or equal to 5% of the thickness of the first part.
13. The manufacturing method of claim 9 , further comprising:
forming a second drift region in the semiconductor substrate, wherein the second drift region is at least partially formed in the second region of the semiconductor substrate; and
forming a source region in the second region of the semiconductor substrate, wherein the source region is formed in the second drift region.
14. The manufacturing method of claim 13 , wherein the patterned conductive structure further comprises a second sub-gate structure disposed on the second region of the semiconductor substrate, wherein the second sub-gate structure is separated from the gate structure and the first sub-gate structure, and the second sub-gate structure is electrically connected to the source region via a second contact structure formed on the second sub-gate structure and the source region.
15. The manufacturing method of claim 9 , further comprising:
forming a sidewall spacer layer on sidewalls of the gate structure and the first sub-gate structure, wherein a part of the sidewall spacer layer is disposed between the gate structure and the first sub-gate structure.