IP Library Granted Patent US 9,691,704
Granted Patent B1
US 9,691,704 · App. 15/175,299 · Granted Jun 27, 2017

Semiconductor structure and method for manufacturing the same

Inventors: Kuo-Chih Lai (Tainan, TW); Chia-Chang Hsu (Kaohsiung, TW); Nien-Ting Ho (Tainan, TW); Ching-Yun Chang (Tainan, TW); Yen-Chen Chen (Tainan, TW); Shih-Min Chou (Tainan, TW); Yun-Tzu Chang (Kaohsiung, TW); Yang-Ju Lu (Changhua, TW); Wei-Ming Hsiao (Miaoli County, TW); Wei-Ning Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L23/528H01L21/32133H01L21/7682H01L21/7685H01L21/76816H01L21/76877H01L23/5226H01L23/5329
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Quick Facts
Patent No.
US 9,691,704
App. No.
15/175,299
Granted
Jun 27, 2017
Kind
B1
Abstract

A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

Claims (35)

1. A semiconductor structure, comprising:

a first wire level comprising a first conductive feature;

a second wire level disposed on the first wire level, the second wire level comprising a second conductive feature and a third conductive feature; and

a via level disposed between the first wire level and the second wire level, the via level comprising a via connecting the first conductive feature and the second conductive feature;

wherein there is a first air gap between the first conductive feature and the second conductive feature, there is a second air gap between the second conductive feature and the third conductive feature, the first air gap comprises a portion in the via level and between the first conductive feature and the second conductive feature, and the first air gap and the second air gap are linked.

2. The semiconductor structure according to claim 1 , wherein the first air gap surrounds the via.

3. The semiconductor structure according to claim 1 , wherein there is a third air gap between the first conductive feature and the third conductive feature, and the third air gap and the first and second air gaps are linked.

4. The semiconductor structure according to claim 1 , further comprising:

a first barrier layer disposed on the first wire level, wherein the via is through the first barrier layer; and

a second barrier layer disposed on the second wire level.

5. The semiconductor structure according to claim 1 , wherein the first wire level further comprises a dielectric surrounding the first conductive feature, the second wire level further comprises a dielectric surrounding the second conductive feature and the third conductive feature, and the via level further comprises a dielectric surrounding the via.

6. A method for manufacturing a semiconductor structure, comprising:

providing a preliminary structure, the preliminary structure comprising a first wire level, the first wire level comprising a first conductive feature;

forming a first sacrificial place-holding feature in a via level above the first wire level;

forming a second sacrificial place-holding feature in a second wire level above the via level;

forming a via of the via level and forming a second conductive feature and a third conductive feature of the second wire level, wherein the via connects the first conductive feature and the second conductive feature; and

removing the first sacrificial place-holding feature and the second sacrificial place-holding feature to form a first air gap and a second air gap, wherein the first air gap is between the first conductive feature and the second conductive feature, the second air gap is between the second conductive feature and the third conductive feature, the first air gap comprises a portion in the via level and between the first conductive feature and the second conductive feature, and the first air gap and the second air gap are linked.

7. The method according to claim 6 ,

wherein forming the first sacrificial place-holding feature comprises:

forming a layer of a sacrificial place-holding material on the preliminary structure, the layer of the sacrificial place-holding material having a first opening configured for the via; and

wherein forming the second sacrificial place-holding feature comprises:

forming a dielectric material on the layer of the sacrificial place-holding material, the dielectric material filling into the first opening;

forming a second opening through the dielectric material; and

filling the sacrificial place-holding material into the second opening.

8. The method according to claim 7 , wherein the sacrificial place-holding material comprises a metal element.

9. The method according to claim 7 , wherein the sacrificial place-holding material comprises at least one selected from the group consisting of: TiN, Ti, Ni, Co, TaN, Ta, Al, TiAl, and TaAl.

10. The method according to claim 7 , wherein forming the second conductive feature, the third conductive feature and the via comprises:

forming a third opening and a fourth opening in the dielectric material, wherein the third opening is configured for the second conductive feature and the via, and the fourth opening is configured for the third conductive feature; and

filling a conductive material into the third opening and the fourth opening.

11. The method according to claim 7 , wherein the preliminary structure further comprises a dielectric surrounding the first conductive feature, and a remained portion of the dielectric material forms a dielectric surrounding the via and a dielectric surrounding the second conductive feature and the third conductive feature.

12. The method according to claim 6 , wherein removing the first sacrificial place-holding feature and the second sacrificial place-holding feature uses an etchant.

13. The method according to claim 12 , wherein the etchant is selected from the group consisting of: SPM (H 2 SO 4 —H 2 O 2 ), HPM (HCl—H 2 O 2 —H 2 O), and APM (NH 4 OH—H 2 O 2 —H 2 O).

14. The method according to claim 6 , wherein removing the first sacrificial place-holding feature and the second sacrificial place-holding feature further forms a third air gap between the first conductive feature and the third conductive feature, and the third air gap and the first and second air gaps are linked.

15. The method according to claim 6 , wherein the preliminary structure further comprises a first barrier layer disposed on the first wire level, and the method further comprises:

forming a second barrier layer on the second wire level, wherein the first sacrificial place-holding feature and the second sacrificial place-holding feature are removed through a through hole of the second barrier layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2016
From: LAI, KUO-CHIH; HSU, CHIA-CHANG; HO, NIEN-TING; CHANG, CHING-YUN; CHEN, YEN-CHEN; CHOU, SHIH-MIN; CHANG, YUN-TZU; LU, YANG-JU; HSIAO, WEI-MING; CHEN, WEI-NING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 038828/0882 →
Priority Claims (1)
CN 2016 1 0260924 · Apr 25, 2016 · national