Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
1. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells, the memory cells being connected to a word line, the memory cells being connected to bit lines, respectively, and each of the memory cells being capable of storing n values (n is a natural number equal to or larger than 3); and
a control circuit which controls potentials of the word line and the bit lines according to input data and writes data to the memory cells,
wherein the control circuit executes first to k-th write sequences (k is a natural number equal to or larger than 2) for the memory cells, each write sequence including a plurality of program operations and a plurality of verify operations for verifying threshold voltages of the memory cells, the program operations and the verify operations being repeated alternately, data being written to the memory cells together, and each of the memory cells being set to one of the n values in the write sequences,
the control circuit raises a program voltage in increments of ΔVpgm in the program operations,
threshold distributions in the first to k-th write sequences get narrower in order, and
ΔVpgm in the first k-th write sequences fulfill the following expression:
ΔVpgm in the first write sequence>ΔVpgm in the second write sequence>ΔVpgm in the k-th write sequence.
2. The semiconductor memory device according to claim 1 , wherein the control circuit verifies the threshold voltages of the memory cells by applying a verify voltage to the word line in each of the verify operations.
3. The semiconductor memory device according to claim 1 , wherein the memory cells constitute a NAND flash memory.
4. The semiconductor memory device according to claim 1 , wherein the threshold distributions in the first to k-th write sequences fulfill the following expression: a first width >a second width > . . . >a k-th width,
where the first width is a width of one of threshold distributions in the first write sequence, the second width is a width of one of threshold distributions in the second write sequence, and the k-th width is a width of one of threshold distributions in the k-th write sequence.
5. The semiconductor memory device according to claim 1 , wherein the control circuit executes verify operations after each of the program operations, and applies verify voltages to the word line in the verify operations.
6. The semiconductor memory device according to claim 1 , wherein verify levels of the verify operations fulfill the following expression:
a first verify level of the first write sequence <a second verify level of the second write sequence < . . . <a k-th verify level of the k-th write sequence.