Stacked semiconductor device
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.
1. A memory device for coupling with a logic integrated circuit (IC) chip having a first data input/output (I/O) circuit for transferring data signals, the memory device comprising:
a first memory IC chip having a second data I/O circuit formed at a first location on the first memory IC chip;
a second memory IC chip stacked with the first memory IC chip, the second memory IC chip including a third data I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip; and
a link selectively coupled to the second data I/O and the third I/O, the link for establishing a point-to-point data connection between the first data I/O circuit and one of the second data I/O circuit or the third data I/O circuit.
2. The memory device according to claim 1 , wherein the first and second memory IC chips comprise DRAM memory devices, and wherein the data signals represent information to be stored in one of the DRAM memory devices.
3. The memory according to claim 2 , wherein the logic IC chip comprises a DRAM memory controller.
4. The memory according to claim 1 , wherein the link comprises a through-silicon-via (TSV).
5. The memory according to claim 1 , wherein the second data I/O circuit of the first memory IC is vertically aligned with the third data I/O circuit of the second memory IC, and the link is for selectively connecting the first data I/O circuit to one of the third data I/O circuit and the second data I/O circuit.
6. The memory according to claim 5 , wherein the link connects to the third data I/O circuit via a programmable fuse.
7. The memory according to claim 1 , wherein the stacking of the first memory IC is laterally offset with respect to the second memory IC such that the third data I/O circuit is misaligned with the second data I/O circuit.
8. The memory device according to claim 1 , wherein each of the first and second memory IC chips further includes respective control/address I/O circuits, and wherein the memory device further comprises a multi-drop link coupled to the respective control/address I/O circuits.
9. The memory device according to claim 1 , wherein the first and second memory IC chips comprise non-volatile memory devices.
10. A memory comprising:
a logic integrated circuit (IC) chip having a first data input/output (I/O) circuit;
a first memory IC chip stacked with the logic IC chip and having a second data I/O circuit formed at a first location on the first memory IC chip;
a second memory IC chip stacked with the first memory IC chip, the second memory chip including a third data I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip; and
a point-to-point link selectively connecting the first data I/O circuit to the third data I/O circuit.
11. The memory according to claim 10 , wherein the first and second memory IC chips comprise DRAM memory devices.
12. The memory according to claim 10 , wherein the logic IC chip comprises a DRAM memory controller.
13. The memory according to claim 10 , wherein the point-to-point link comprises a through-silicon-via (TSV).
14. The memory according to claim 10 , wherein the second data I/O circuit of the first memory IC is vertically aligned with the third data I/O circuit of the second memory IC, and the point-to-point link selectively connects the first data I/O circuit to one of the third data I/O circuit and the second data I/O circuit.
15. The memory according to claim 14 , wherein the point-to-point link connects to the third data I/O circuit via a programmable fuse.
16. The memory according to claim 10 , wherein the stacking of the first memory IC is laterally offset with respect to the second memory IC such that the third data I/O circuit vertically aligns with the first data I/O circuit, and the second data I/O circuit is offset from the first data I/O circuit.
17. The memory according to claim 10 , wherein each of the logic and first and second memory IC chips further includes respective control/address I/O circuits, and wherein the memory further comprises a multi-drop link coupled to the respective control/address I/O circuits.
18. The memory according to claim 10 , wherein the first and second memory IC chips comprise non-volatile memory devices.
19. A method of operating a memory having a memory controller IC chip stacked with multiple memory device IC chips, the method comprising:
transferring data signals between the memory controller IC chip and each of the multiple memory device IC chips along through-silicon via point-to-point links, each of the through-silicon via point-to-point links being selectively connected between the memory controller IC chip and a separate one of the multiple memory device IC chips; and
transferring control/address (C/A) signals between the memory controller IC chip and each of the memory device IC chips along at least one through-silicon via multi-drop link.
20. The method according to claim 19 , wherein the transferring data signals and transferring C/A signals is carried out in accordance with a DRAM protocol.