Charge packet signal processing using pinned photodiode devices
An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.
1. An image sensor, comprising:
an image pixel comprising a first pinned photodiode coupled to a pixel output line; and
analog-to-digital conversion (ADC) circuitry coupled to the pixel output line, wherein the ADC circuitry comprises:
a second pinned photodiode;
a comparator with first and second inputs;
a sampling transistor;
a first capacitive node that is coupled between the second pinned photodiode the first input of the comparator; and
a second capacitive node that is coupled between the sampling transistor and the second input of the comparator.
2. The image sensor defined in claim 1 , further comprising:
a first capacitor coupled between the first capacitive node and the first input of the comparator;
a first switch coupling the first capacitor to a first voltage supply;
a second capacitor coupled between the second capacitive node and the second input of the comparator; and
a second switch coupling the second capacitor to a second voltage supply.
3. The image sensor defined in claim 1 , further comprising:
a level shifter coupled between the pixel output line and the sampling transistor.
4. The image sensor defined in claim 1 , wherein the comparator has an output terminal, the image sensor further comprising:
a counter with an enable port that is coupled to the comparator output terminal.
5. The image sensor defined in claim 1 , further comprising:
a third pinned photodiode coupled to the second capacitive node.
6. The image sensor defined in claim 1 , further comprising:
a third pinned photodiode coupled to the first capacitive node;
a first transfer transistor coupled between the second pinned photodiode and the first capacitive node; and
a second transfer transistor coupled between the third pinned photodiode and the first capacitive node.
7. The image sensor defined in claim 6 , wherein a gate terminal of the first transfer transistor is coupled to a gate terminal of the second transfer transistor.
8. The image sensor defined in claim 6 , further comprising:
a voltage supply terminal;
a first fill transistor coupled between the voltage supply terminal and the second pinned photodiode; and
a second fill transistor coupled between the voltage supply terminal and the third pinned photodiode.