IP Library › Granted Patent US 10,180,887
Granted Patent B1
US 10,180,887 · App. 15/176,156 · Granted Jan 15, 2019

Adaptive power cycle sequences for data recovery

Inventors: Rolando H. Bruce (South San Francisco, CA); Richard A. Cantong (Cabuyao Laguna, PH); Marizonne O. Fuentes (Leyte, PH)
Assignee: BiTMICRO LLC
G06F11/1471G06F3/0619G06F3/0652G06F3/0653G06F3/0673G06F12/0804G06F2201/805G06F2201/82G06F2201/85G06F2212/1032
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Quick Facts
Patent No.
US 10,180,887
App. No.
15/176,156
Granted
Jan 15, 2019
Kind
B1
Abstract

The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.

Claims (67)

1. A storage apparatus, comprising:

a peripheral interface for coupling the storage apparatus to a host;

a local processor coupled to the peripheral interface;

storage media, comprising:

cache storage coupled to the peripheral interface;

nonvolatile memory (NVM) coupled to the peripheral interface via a memory controller coupled to the peripheral interface; and

a local memory, accessible to the local processor the local memory includes processor executable instructions that, when executed by the local processor, cause the storage apparatus to perform operations including:

providing, in the cache storage, a free list block comprising free list entries pointing to free list sections in the nonvolatile memory;

scanning the free list block to identify logical free list sections containing user data, wherein a logical free list section comprises a free list section associated with a logical block address (LBA) and wherein each logical free list section containing user data requires an update of a directory block (DB) and an information directory block (IDB) associated with the logical free list section;

responsive to identifying a particular logical free list section containing user data, performing a power cycle recovery of an IDB associated with the particular logical free list section and a power cycle recovery of a DB associated with the particular logical free list section;

scanning each free list section that is pointed to by a free list entry;

responsive to identifying an unassigned free list section, performing a power cycle recovery sequence for an IDB associated with the unassigned free list section, wherein an unassigned free list section comprises a free list section not associated with an LBA; and

responsive to determining that the unassigned free list section is in an invalid state, erasing the unassigned free list section.

2. The storage device of claim 1 , wherein the operations include:

storing a control block comprising DBs wherein the DBs include addresses of data blocks.

3. The storage device of claim 1 , wherein each free list entry points to a section in the nonvolatile memory.

4. The storage device of claim 1 , wherein each free list entry includes an associated section index that points to an associated section.

5. The storage device of claim 1 , wherein each free list section includes a non-volatile memory block.

6. The storage device of claim 1 , wherein performing the power cycle recovery of the IDB associated with the particular logical free list section includes:

providing the IDB associated with the particular logical free list section to the cache storage, wherein a current state of the particular logical free list section is a used state;

locating, in the cache storage, an IDB entry associated with the particular logical free list section;

checking an invalid bit map flag of the IDB entry associated with the particular logical free list section; and

if the invalid bit map flag does not reflect the used state of the particular logical free list section, then setting the invalid bit map flag to a value reflecting the used state of the particular logical free list section.

7. The storage device of claim 1 , wherein performing the power cycle recovery of the DB associated with the particular logical free list section includes:

reading a logical block address and a displaced physical block address associated with the particular logical free list section;

determining whether user data in the particular logical free list section is error free;

responsive to determining the user data in the particular logical free list section is error free, providing the DB associated with the particular logical free list section to the cache storage;

checking a directory entry in the DB associated with the particular logical free list section, wherein the directory entry is associated with the particular logical free list section;

responsive to detecting that a physical block address in the directory entry does not match the displaced physical block address, comparing a section pointed to by a section index of an entry in a free list block and a section pointed to by the physical block address in the directory entry;

responsive to determining that the section pointed to by the section index is newer than the section pointed to by the physical block address in the directory entry, updating the DB associated with the particular logical free list section; and

responsive to detecting that the section pointed to by the section index is not newer than the section pointed to by the physical block address in the directory entry, replacing the physical block address in the directory entry with the section index.

8. A power cycle recovery method, comprising:

providing, by a storage device, a free list block to cache storage, wherein the free list block includes free list entries pointing to free list sections in a nonvolatile memory;

scanning the free list block to identify logical free list sections containing user data, wherein a logical free list section comprises a free list section associated with a logical block address (LBA) and wherein each logical free list section containing user data requires an update of a directory block (DB) and an information directory block (IDB) associated with the logical free list section;

responsive to identifying a particular logical free list section containing user data, performing a power cycle recovery of an IDB associated with the particular logical free list section and a power cycle recovery of a DB associated with the particular logical free list section;

scanning each free list section that is pointed to by a free list entry;

responsive to identifying an unassigned free list section, performing a power cycle recovery sequence for an IDB associated with the unassigned free list section, wherein an unassigned free list section comprises a free list section not associated with an LBA; and

responsive to determining that the unassigned free list section is in an invalid state, erasing the unassigned free list section.

9. The method of claim 8 , further comprising:

storing a control block comprising DBs wherein the DBs include addresses of data blocks.

10. The method of claim 8 , wherein each free list entry points to a section in the nonvolatile memory.

11. The method of claim 8 , wherein each free list entry includes an associated section index that points to an associated section.

12. The method of claim 8 , wherein each section includes a non-volatile memory block.

13. The method of claim 8 , wherein performing the power cycle recovery of the IDB associated with the particular logical free list section includes:

providing the IDB associated with the particular logical free list section to the cache storage, wherein a current state of the particular logical free list section is a used state;

locating, in the cache storage, an IDB entry associated with the particular logical free list section;

checking an invalid bit map flag of the IDB entry associated with the particular logical free list section; and

if the invalid bit map flag does not reflect the used state of the particular logical free list section, then setting the invalid bit map flag to a value reflecting the used state of the particular logical free list section.

14. The method of claim 8 , wherein performing the power cycle recovery of the DB associated with the particular logical free list section includes:

reading a logical block address and a displaced physical block address associated with the particular logical free list section;

determining whether user data in the particular logical free list section is error free;

responsive to determining the user data in the particular logical free list section is error free, providing the DB associated with the particular logical free list section to the cache storage;

checking a directory entry in the DB associated with the particular logical free list section, wherein the directory entry is associated with the particular logical free list section;

responsive to detecting that a physical block address in the directory entry does not match the displaced physical block address, comparing a section pointed to by a section index of an entry in a free list block and a section pointed to by the physical block address in the directory entry;

responsive to determining that the section pointed to by the section index is newer than the section pointed to by the physical block address in the directory entry, updating the DB associated with the particular logical free list section; and

responsive to detecting that the section pointed to by the section index is not newer than the section pointed to by the physical block address in the directory entry, replacing the physical block address in the directory entry with the section index.

15. An article of manufacture comprising a non-transitory computer-readable medium having stored thereon processor executable instructions, wherein the instructions, when executed by a processor cause the processor to perform operations including:

providing, by a storage device, a free list block to cache storage, wherein the free list block includes free list entries pointing to free list sections in a nonvolatile memory;

scanning the free list block to identify logical free list sections containing user data, wherein a logical free list section comprises a free list section associated with a logical block address (LBA) and wherein each logical free list section containing user data requires an update of a directory block (DB) and an information directory block (IDB) associated with the logical free list section;

responsive to identifying a particular logical free list section containing user data, performing a power cycle recovery of an IDB associated with the particular logical free list section and a power cycle recovery of a DB associated with the particular logical free list section;

scanning each free list section that is pointed to by a free list entry;

responsive to identifying an unassigned free list section, performing a power cycle recovery sequence for an IDB associated with the unassigned free list section, wherein an unassigned free list section comprises a free list section not associated with an LBA; and

responsive to determining that the unassigned free list section is in an invalid state, erasing the unassigned free list section.

16. The article of manufacture of claim 15 , wherein the operations include:

storing a control block comprising a directory block and wherein the directories hold addresses of data blocks.

17. The article of manufacture of claim 15 , wherein each free list entry points to a section in the nonvolatile memory.

18. The article of manufacture of claim 15 , wherein each free list entry includes an associated section index that points to an associated section.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2018
From: BITMICRO NETWORKS, INC
To: BITMICRO LLC
Reel/Frame 044910/0152 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2017
From: BRUCE, ROLANDO H.; CANTONG, RICHARD A.; FUENTES, MARIZONNE O.
To: BITMICRO NETWORKS, INC.
Reel/Frame 044889/0453 →
Continuity (1)
Continuation 13253912 · Oct 5, 2011