Method for error logging
Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.
1. A method for logging errors in a hardware architecture operating a plurality of physically separate computing nodes, the method comprising:
in response to an error within one of the computing nodes, generating, by the computing node, an error interrupt;
in response to the error interrupt, executing an error handling process by a Basic Input/Output System (BIOS) of the computing node, including:
retrieving, by the BIOS, error data from an error register within the computing node, and
writing, by the BIOS, the error data retrieved from the error register to a memory-mapped buffer within the computing node; and
sending the error data from the memory-mapped buffer to a repository of the computing node accessible by an error analyzer in the hardware architecture coupled to but separate from the plurality of computing nodes.
2. The method of claim 1 further comprising retrieving error register contents through Joint Test Action Group (JTAG) and running the error analyzer to analyze at least some of the error register contents and at least some of the error data to determine which component in the hardware architecture needs to be repaired or replaced.
3. The method of claim 1 , wherein retrieving the error data from the error register includes retrieving an identifier of the error register and content of the error register.
4. The method of claim 1 , further comprising: rearming the error register after the error data has been read from the error register.
5. The method of claim 1 , further comprising discarding the error data to be written when the memory-mapped buffer is full.
6. The method of claim 1 , wherein the error interrupt is generated when the error is indicated in the error register.
7. The method of claim 1 , wherein the hardware architecture includes a high performance computing system.
8. A computing device comprising:
a processor;
an error register; and
a Basic Input/Output System (BIOS), wherein, in response to an error in the computing device, the BIOS of the computing device is executed to instruct the processor to:
generate an error interrupt;
in response to the error interrupt, retrieve error data from an error register within the computing device and write the error data retrieved from the error register to a memory-mapped buffer within the computing device; and
send the error data from the memory-mapped buffer to a repository of the computing device accessible by an error analyzer of a management node.
9. The computing device of claim 8 , wherein the error analyzer is to analyze the error data received from the memory-mapped buffer and error register contents retrieved through Joint Test Action Group (JTAG) to determine which component in a computing system needs to be repaired or replaced.
10. The computing device of claim 8 , wherein the error data retrieved from the error register includes an identifier of the error register and content of the error register.
11. The computing device of claim 8 , wherein, after the error data is retrieved from the error register, the BIOS is to instruct the processor to rearm the error register.
12. The computing device of claim 8 , wherein the BIOS is to instruct the processor to: discard the error data to be written when the memory-mapped buffer is full.
13. A computing system comprising:
a management node; and
a plurality of computing nodes, each computing node having a Basic Input/Output System (BIOS), a processor, an error register, and a memory-mapped buffer,
wherein, in response to an error in one of the computing nodes, the BIOS of the computing node is executed to instruct the processor within of the computing node to:
generate an error interrupt;
in response to the error interrupt, retrieve error data from the error register of the computing node, and write the error data retrieved from the error register to the memory-mapped buffer of the computing node; and
send the error data from the memory-mapped buffer to a repository of the computing node accessible by an error analyzer of the management node.
14. The computing system of claim 13 , wherein the management node is to: retrieve error register contents through Joint Test Action Group (JTAG) and run the error analyzer to analyze the error register contents and the error data to determine which component in the computing system needs to be repaired or replaced.
15. The computing system of claim 13 , wherein the error data retrieved from the error register of the computing node includes an identifier of the error register of the computing node and content of the error register of the computing node.
16. The computing system of claim 13 , wherein, after the error data is retrieved from the error register of the computing node the BIOS of the computing node is to instruct the processor of the computing node to rearm the error register of the computing node.
17. The computing system of claim 13 , wherein the BIOS of the computing node is to instruct the processor of the computing node to: discard the error data to be written when the memory-mapped buffer of the computing node is full.