Doherty amplifiers with minimum phase output networks

1. A Doherty amplifier comprising:

an output combining network with N combining network inputs, multiple summing nodes, and a combining network output, wherein N is an integer greater than two, and the output combining network is configured to combine signals received at the N combining network inputs into a combined signal that is provided at the combining network output;

a main amplifier path with an output coupled to a first combining network input of the N combining network inputs, wherein the main amplifier path includes a main amplifier stage and a first output matching network coupled to an output of the main amplifier stage, and wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a first RF signal conveyed through the main amplifier path; and

N−1 peaking amplifier paths, wherein each peaking amplifier path has an output that is coupled to one of N−1 different combining network inputs of the N combining network inputs, and wherein each of the N−1 peaking amplifier paths includes a peaking amplifier stage and an output matching network coupled to an output of the peaking amplifier stage, wherein the output matching network of each of N-2 of the peaking amplifier paths imparts a phase delay of 90 degrees and provides a single impedance inversion to an RF signal conveyed through each of the N-2 peaking amplifier paths, and wherein a lowest-order peaking amplifier path is coupled to a lowest-order combining network input of the N combining network inputs, and

wherein the multiple summing nodes of the output combining network include a final summing node and N-2 intermediate summing nodes, wherein the final summing node is coupled to the combining network output and is directly coupled to the first combining network input, the N-2 intermediate summing nodes each are directly coupled to a different one of N-2 other combining network inputs of the N combining network inputs, and

wherein the output combining network further includes N-2 impedance transformers each coupled between different sets of adjacent summing nodes of the multiple summing nodes, and an offset line coupled between the lowest-order combining network input and a lowest-order summing node of the N-2 intermediate summing nodes.

2. The Doherty amplifier of claim 1 , further comprising:

an N-way power divider that includes a power divider input and N power divider outputs, wherein each of the N power divider outputs is coupled to one path of the main amplifier path and the N−1 peaking amplifier paths, and the N-way power divider is configured to divide an input power of an input RF signal received at the power divider input into N portions of the input RF signal, and to provide the N portions of the input RF signal to the N power divider outputs.

3. The Doherty amplifier of claim 2 , wherein the N-way power divider further includes a plurality of delay line elements, which impart various phase delays to the N portions of the input RF signal, wherein, starting with a lowest-order delay line element that is coupled to an input to the lowest-order peaking amplifier path, successively higher-order delay line elements each impart an additional 90 degree phase delay to the portions of the input RF signal received by each of the delay line elements.

4. The Doherty amplifier of claim 1 , further comprising N input matching networks, wherein each of the N input matching networks is coupled to an input to one of the main amplifier stage and the N−1 peaking amplifier stages.

5. The Doherty amplifier of claim 1 , wherein the output combining network further includes an additional impedance transformer coupled between the final summing node and the combining network output.

6. The Doherty amplifier of claim 1 , wherein N equals 3.

7. The Doherty amplifier of claim 1 , wherein N is equal to or greater than 4.

8. A Doherty amplifier comprising:

an output combining network with first, second, third, and fourth combining network inputs, a combining network output, a first summing node directly coupled to the first combining network input, a second summing node directly coupled to the second combining network input, a third summing node directly coupled to the third combining network input, a first impedance transformer coupled between the first and second summing nodes, a second impedance transformer coupled between the second and third summing nodes, and an offset line coupled between the fourth combining network input and the third summing node, wherein the output combining network is configured to combine signals received at the combining network inputs into a combined signal that is provided at the combining network output;

a main amplifier path with an output coupled to the first combining network input, wherein the main amplifier path includes a main amplifier stage and a main output matching network coupled to an output of the main amplifier stage, and wherein the main output matching network imparts a phase delay and provides a single impedance inversion to a main RF signal conveyed through the main amplifier path;

first, second, and third peaking amplifier paths, each with an output coupled to a different one of the second, third, and fourth combining network inputs, wherein each of the peaking amplifier paths includes a peaking amplifier stage and a peaking output matching network coupled to an output of the peaking amplifier stage, and wherein each of a first and second peaking output matching network of the first and second peaking amplifier paths imparts a phase delay and provides a single impedance inversion to a peaking RF signal conveyed through the first and second peaking amplifier paths to which each of the first and second peaking output matching network is coupled.

9. The Doherty amplifier of claim 8 , wherein the phase delay imparted by each of the main output matching network and the first and second peaking output matching networks is 90 degrees.

10. The Doherty amplifier of claim 8 , further comprising:

an power divider that includes a power divider input and first, second, third, and fourth power divider outputs, wherein the first power divider output is coupled to the main amplifier path, the second power divider output is coupled to the first peaking amplifier path, the third power divider output is coupled to the second peaking amplifier path, and the fourth power divider output is coupled to the third peaking amplifier path, and the power divider is configured to divide an input power of an input RF signal received at the power divider input into the main RF signal and first, second, and third peaking RF signals, and to provide the main RF signal to the first power divider output, the first peaking RF signal to the second power divider output, the second peaking RF signal to the third power divider output, and the third peaking RF signal to the fourth power divider output.

11. The Doherty amplifier of claim 10 , wherein the power divider further includes first, second, and third delay line elements, wherein the first delay line element is coupled to the first power divider output and imparts a first delay to the main RF signal, the second delay line element is coupled to the second power divider output and imparts a second delay to the first peaking RF signal, and the third delay line element is coupled to the third power divider output and imparts a third delay to the second peaking RF signal, wherein the second delay is less than the first delay, and the third delay is less than the second delay.

12. The Doherty amplifier of claim 11 , wherein the second delay is 90 degrees less than the first delay, and the third delay is 90 degrees less than the second delay.

13. The Doherty amplifier of claim 11 , wherein the power divider further includes a fourth delay line element that imparts a fourth delay to the third peaking RF signal, wherein the fourth delay is 90 degrees less than the third delay.

14. A Doherty amplifier comprising:

a main amplifier path with an input and an output;

N−1 peaking amplifier paths, wherein each peaking amplifier path has an input and an output, and wherein N is greater than two; and

an output combining network with

a combining network output,

N combining network inputs, with a first combining network input coupled to the output of the main amplifier path, a lowest-order combining network input coupled to a lowest-order peaking amplifier path of the N−1 peaking amplifier paths, and N-2 additional combining network inputs coupled to other paths of the N−1 peaking amplifier paths,

multiple summing nodes, including a final summing node coupled to the combining network output and directly coupled to the first combining network input, and N-2 intermediate summing nodes each directly coupled to a different one of the N-2 additional combining network inputs, and

an offset line coupled between the lowest-order combining network input and a lowest-order summing node of the N-2 intermediate summing nodes, and

wherein a longest phase delay imparted by the output combining network on a peaking RF signal between the lowest-order combining network input and the final summing node is greater than all other phase delays imparted by the output combining network on any other RF signal provided to the first combining network input and the N-2 additional combining network inputs.

15. The Doherty amplifier of claim 14 , wherein the output combining network further includes N-2 impedance transformers each coupled between different sets of adjacent summing nodes of the multiple summing nodes.

16. The Doherty amplifier of claim 14 , wherein:

the main amplifier path includes a main amplifier stage and a first output matching network coupled to an output of the main amplifier stage, wherein the first output matching network imparts a phase delay of 90 degrees and provides a single impedance inversion to a first RF signal conveyed through the main amplifier path; and

each of the N−1 peaking amplifier paths includes a peaking amplifier stage and an output matching network coupled to an output of the peaking amplifier stage, wherein the output matching network of each of N-2 of the peaking amplifier paths imparts a phase delay of 90 degrees and provides a single impedance inversion to an RF signal conveyed through each of the N-2 peaking amplifier paths.

17. The Doherty amplifier of claim 14 , wherein:

N equals 3;

the longest phase delay is at least 90 degrees plus an additional phase delay imparted by the offset line; and

all other phase delays imparted by the output combining network on any other RF signal are less than the longest phase delay by at least the phase delay imparted by the offset line.

18. The Doherty amplifier of claim 14 , wherein:

N is equal to or greater than 4;

the longest phase delay is at least 180 degrees plus an additional phase delay imparted by the offset line; and

all other phase delays imparted by the output combining network on any other RF signal are less than the longest phase delay by at least the phase delay imparted by the offset line.

19. The Doherty amplifier of claim 14 , further comprising:

an N-way power divider that includes a power divider input and N power divider outputs, wherein each of the N power divider outputs is coupled to one path of the main amplifier path and the N−1 peaking amplifier paths, and the N-way power divider is configured to divide an input power of an input RF signal received at the power divider input into N portions of the input RF signal, and to provide the N portions of the input RF signal to the N power divider outputs.

20. The Doherty amplifier of claim 19 , wherein the N-way power divider further includes a plurality of delay line elements, which impart various phase delays to the N portions of the input RF signal, wherein, starting with a lowest-order delay line element that is coupled to an input to the lowest-order peaking amplifier path, successively higher-order delay line elements each impart an additional 90 degree phase delay to the portions of the input RF signal received by each of the delay line elements.

21. The Doherty amplifier of claim 14 , wherein the output combining network further includes an additional impedance transformer coupled between the final summing node and the combining network output.