Tipless transistors, short-tip transistors, and methods and circuits therefor
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
1. An integrated circuit, comprising:
a first deeply depleted channel transistor formed in the substrate and having a first source-drain current path coupled between a first and a second node, the first deeply depleted channel transistor having a first source drain vertical doping profile with a first extension region that extends in a lateral direction under a gate electrode of the first deeply depleted channel transistor, the first deeply depleted channel transistor being configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first deeply depleted channel transistor having a first drawn gate length of less than one micron; and
a second deeply depleted channel transistor formed in the substrate and having a second source-drain current path coupled between the first node and the second node, the second deeply depleted channel transistor having a second source drain vertical doping profile with a second extension region of which dopant concentration is less than dopant concentration of the first extension region, the second deeply depleted channel transistor being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the second deeply depleted channel transistor having a second drawn gate length of less than one micron and same channel doping profile as a channel doping profile of the first deeply depleted channel transistor.
2. The integrated circuit of claim 1 , wherein:
the first deeply depleted channel transistor having a first source and drain having the first source drain vertical doping profile doped to a first conductivity type, a first substantially undoped channel region, and a first highly doped screening region of the second conductivity type formed below the first substantially undoped channel region.
3. The integrated circuit of claim 1 , wherein:
the second deeply depleted channel transistor having a second source and drain having the second source drain vertical doping profile doped to a first conductivity type, a second substantially undoped channel region, and a second highly doped screening region of the second conductivity type formed below the second substantially undoped channel region.
4. The integrated circuit of claim 1 , further including:
a delay circuit configured to delay an electrical signal and comprising at least the second deeply depleted channel transistor.
5. The integrated circuit of claim 4 , further including:
a logic gate configured to logically combine signals at a plurality of gate inputs to generate a gate output signal; and the delay circuit is coupled to a first gate input of the logic gate.
6. The integrated circuit of claim 5 , further including:
a pulse generator that includes the logic gate having a second gate input coupled to receive an input signal, and
the delay circuit is coupled to receive the input signal and has a delay circuit output coupled to the first gate input.
7. The integrated circuit of claim 6 , wherein:
the pulse generator further includes the logic gate having a third gate coupled to receive an enable signal that enables and disables the pulse generator circuit.
8. The integrated circuit of claim 6 , further including:
a flip-flop circuit comprising a plurality of latches arranged in series, each latch having a clocked input,
passgates coupled in parallel to an input of the flip-flop circuit, and
the delay circuit is coupled to an input of one of the passgates.
9. The integrated circuit of claim 6 , further including:
a memory cell array;
sense amplifier circuits coupled to the memory cell array and configured to sense data values from memory cells of the memory cell array, the sense amplifier circuits being enabled in response to a sense amplifier control signal;
a control circuit configured to generate an initial sense amplifier control signal; and
the delay circuit is configured to delay the initial sense amplifier control signal to generate the sense amplifier control signal.
10. The integrated circuit of claim 5 , further including:
a timing control circuit configured to generate a periodic timing clock for the integrated circuit, and comprising the delay circuit; wherein
the timing control circuit is selected from the group of: a phase locked loop circuit and a delay locked loop circuit.
11. The integrated circuit of claim 1 , wherein:
the first deeply depleted channel transistor has the first drawn gate length of less than 0.5 micron; and
the second deeply depleted channel transistor has the second drawn gate length of less than 0.5 micron.