Vertical Schottky barrier FET
A method for fabricating a vertical Schottky barrier transistor includes forming fin trenches through a dielectric layer and a dummy gate stack on a substrate to expose an underlying semiconductor material. The dummy gate stack includes a bottom spacer, a dummy gate layer and a top spacer layer. Fins are epitaxially grown in the fin trenches from the underlying semiconductor material. The dummy gate layer is removed and forms a gate structure about the fins including a gate dielectric and a gate conductor. An interlevel dielectric (ILD) layer is deposited. A top of the fins is exposed to form a channel contact opening. A contact trench is formed through the ILD layer and into the underlying semiconductor material. A cavity is formed in the underlying semiconductor material below the bottom spacer layer. The cavity, the contact trench and the channel contact opening are filled with a conductive fill.
1. A method for fabricating a vertical Schottky barrier transistor, comprising:
forming fin trenches through a dielectric layer and a dummy gate stack on a substrate to expose an underlying semiconductor material, the dummy gate stack including a bottom spacer, a dummy gate layer and a top spacer layer;
epitaxially growing fins in the fin trenches from the underlying semiconductor material;
removing the dummy gate layer and forming a gate structure about the fins including a gate dielectric and a gate conductor;
depositing an interlevel dielectric (ILD) layer;
exposing a top of the fins to form a channel contact opening;
forming a contact trench through the ILD layer and into the underlying semiconductor material;
forming a cavity in the underlying semiconductor material below the bottom spacer layer; and
filling the cavity, the contact trench and the channel contact opening with a conductive fill.
2. The method as recited in claim 1 , wherein the underlying semiconductor material of the substrate includes a sacrificial semiconductor layer formed between materials of higher etch selectivity.
3. The method as recited in claim 1 , wherein the underlying semiconductor material of the substrate includes a semiconductor layer formed on a buried dielectric layer of a semiconductor-on-insulator substrate.
4. The method as recited in claim 1 , wherein the dummy gate layer includes amorphous silicon, and the method further comprises: oxidizing the amorphous silicon in the dummy gate layer to form a thin oxide to permit removal of the dummy gate layer.
5. The method as recited in claim 1 , wherein the conductive fill includes a metal which forms a Schottky barrier with a channel formed by the fin.
6. The method as recited in claim 1 , further comprising forming a gate contact that lands on the gate conductor through the ILD layer.
7. The method as recited in claim 2 , wherein the materials of higher etch selectivity include the bottom spacer layer and an etch stop layer formed in the substrate.
8. A method for fabricating a vertical Schottky barrier transistor, comprising:
forming fin trenches through a dielectric layer and a dummy gate stack on a substrate to expose an underlying semiconductor material, the dummy gate stack including a bottom spacer, a dummy gate layer and a top spacer layer;
epitaxially growing fins in the fin trenches from the underlying semiconductor material;
recessing the fins into the fin trenches;
forming a dielectric cap in the fin trenches on the fins;
removing the dielectric layer to expose the cap and a portion of the fin;
forming spacers on the cap and the portion of the fin;
etching the top spacer layer and the dummy gate layer below the spacers;
removing the dummy gate layer;
conformally depositing a gate dielectric and a metal on exposed sidewalls of the fins;
forming a gate conductor;
depositing an interlevel dielectric (ILD) layer;
exposing a top of the fins by removing the dielectric caps to form a channel contact opening;
forming a contact trench through the ILD layer and into the underlying semiconductor material;
forming a cavity in the underlying semiconductor material below the bottom spacer layer; and
filling the cavity, the contact trench and the channel contact opening with a conductive fill.
9. The method as recited in claim 8 , wherein the underlying semiconductor material of the substrate includes a sacrificial semiconductor layer formed between materials of higher etch selectivity.
10. The method as recited in claim 8 , wherein the underlying semiconductor material of the substrate includes a semiconductor layer formed on a buried dielectric layer of a semiconductor-on-insulator substrate.
11. The method as recited in claim 8 , wherein the dummy gate layer includes amorphous silicon, and the method further comprises: oxidizing the amorphous silicon in the dummy gate layer to form a thin oxide to permit removal of the dummy gate layer.
12. The method as recited in claim 8 , wherein the conductive fill includes a metal which forms a Schottky barrier with a channel formed by the fin.
13. The method as recited in claim 8 , further comprising forming a gate contact that lands on the gate conductor through the ILD layer.
14. The method as recited in claim 9 , wherein the materials of higher etch selectivity include the bottom spacer layer and an etch stop layer formed in the substrate.