Pulse width modulator for DC/DC converters

1. A pulse width modulator for a single-ended primary inductance converter (SEPIC) that receives a D.C. input voltage at an input voltage terminal and which produces a D.C. output voltage at an output voltage terminal, the D.C. output voltage being different in magnitude from the D.C. input voltage, the pulse width modulator comprising:

a first comparator comprising:

a first input coupled to the input voltage terminal of the SEPIC;

a second input coupled to a reference voltage; and

an output,

the first comparator being configured to provide an output signal having two possible values, responsive to whether a voltage at the SEPIC input voltage terminal is greater than or less than the reference voltage;

a second comparator having first and second inputs and an output;

an error amplifier having a first input coupled to the SEPIC output voltage terminal, a second input coupled to the reference voltage and an output coupled to the second input of the second comparator;

an oscillator having a control input coupled to the output of the first comparator and an output, the oscillator being configured to generate a first periodic signal having a first frequency and generate a second periodic signal having a second frequency, responsive to the output signal from the first comparator, the first frequency is greater than the second frequency;

a voltage ramp generator having an input coupled to the output of the oscillator and an output coupled to the first input of the second comparator, the voltage ramp generator generating at its output a first voltage ramp signal in response to the oscillator providing the first periodic signal to the voltage ramp generator and a second voltage ramp signal responsive to the oscillator providing the second periodic signal to the voltage ramp generator;

a flip-flop having a reset input coupled to the output of the second comparator, a set input coupled to the output of the oscillator and an output coupled to a control terminal of a SEPIC switch of the SEPIC,

wherein a product of cycle energy and operating frequency of the SEPIC does not change when the operating frequency of the SEPIC changes from the first frequency to the second frequency.

2. The pulse width modulator of claim 1 , wherein a ratio of the first frequency to the second frequency is K, and a peak voltage of the second voltage ramp signal is greater than a peak voltage of the first voltage ramp signal by a square root of K.

3. The pulse width modulator of claim 2 , wherein a slope of the second voltage ramp signal is decreased, relative to a slope of the first voltage ramp signal, by a factor of the square root of K, and a duty cycle of the second voltage ramp signal is equal to a duty cycle of the first voltage ramp signal divided by the square root of K.

4. A power supply comprising:

a single-ended primary-inductance converter (SEPIC) having an input voltage terminal, an output voltage terminal, a reference voltage terminal and a switch configured to connect and disconnect one end of a primary inductance having first and second ends, to the reference voltage terminal;

a controller coupled to the switch and providing a pulse train thereto, the controller determines a duty cycle and frequency at which the switch operates, the controller comprising:

a first comparator having a first input coupled to the input voltage terminal of the SEPIC, a second input coupled to a reference voltage and an output, the first comparator configured to provide a signal at its output that has two possible states, the states being determined by the first comparator responsive to whether a voltage at the SEPIC input voltage terminal is greater than or less than the reference voltage;

a second comparator having first and second inputs and an output;

an error amplifier having a first input coupled to the SEPIC output voltage terminal, a second input coupled to the reference voltage and an output coupled to the second input of the second comparator;

an oscillator having a control input coupled to the output of the first comparator and an output, the oscillator being configured to generate at its output, a first periodic signal having a first frequency and generate at the output a second periodic signal having a second frequency, the first and second output signals being selectively generated by the oscillator responsive to the state of the signal output from the first comparator, the second frequency being less than the first frequency;

a voltage ramp generator having an input coupled to the output of the oscillator and an output coupled to the first input of the second comparator, the voltage ramp generator generating first and second different voltage ramp signals at its output responsive to a frequency of the signal generated at the output of the oscillator; and

a flip-flop having a reset input coupled to the output of the second comparator, a set input coupled to the output of the oscillator and an output coupled to a control terminal of the SEPIC switch,

wherein a product of cycle energy and operating frequency of the SEPIC does not change when the operating frequency of the SEPIC changes from the first frequency to the second frequency.

5. The power supply of claim 4 , wherein a ratio of the first frequency to the second frequency is K, and a peak voltage of the second voltage ramp signal is greater than a peak voltage of the first voltage ramp signal by the square root of K.

6. The power supply of claim 5 , wherein a slope of the second voltage ramp signal is decreased, relative to a slope of the first voltage ramp signal, by a factor of the square root of K, and a duty cycle of the second voltage ramp signal is equal to the duty cycle of the first voltage ramp signal divided by the square root of K.