Memory first process flow and device

1. A memory device, comprising:

a substrate;

a first charge trapping structure formed on the substrate;

a first memory gate formed on the first charge trapping structure;

a first dielectric formed on a sidewall of the first memory gate;

a second dielectric formed on the substrate; and

a first select gate formed on the second dielectric such that the first select gate and the first dielectric are formed on the sidewall of the first memory gate,

wherein the first dielectric is between:

the first memory gate and the first select gate, and

the first charge trapping structure and the second dielectric; and

wherein the first dielectric is comprised of a plurality of dielectric layers, wherein at least one dielectric layer, of the plurality of dielectric layers is separated from the first charge trapping structure by at least one other dielectric layer of the plurality of dielectric layers.

2. The memory device of claim 1 , wherein the at least one dielectric layer comprises a nitride layer.

3. The memory device of claim 1 , wherein the first charge trapping structure comprises a first layer of material including a nitride.

4. The memory device of claim 3 , wherein the first charge trapping structure comprises a second layer of material and a third layer of material including one or more oxides, wherein the first layer of material is between the second layer of material and the third layer of material.

5. The memory device of claim 1 , wherein at least a portion of the second dielectric is between the select gate and the memory gate.

6. The memory device of claim 1 , further comprising:

a second charge trapping structure formed on the substrate;

a second memory gate formed on the second charge trapping structure;

a third dielectric formed on a sidewall of the second memory gate; and

a second select gate formed on the second dielectric,

wherein the third dielectric is between:

the second memory gate and the second select gate, and

the second charge trapping structure and the second dielectric.

7. The memory device of claim 6 , wherein the first select gate is formed on the first dielectric and the second select gate is formed on the third dielectric.

8. The memory device of claim 6 , wherein the second dielectric is between the first dielectric and the third dielectric.

9. The memory device of claim 6 , wherein the first select gate is between the second select gate and the first dielectric.

10. The memory device of claim 6 , wherein the second select gate is between the first select gate and the third dielectric.

11. A semiconductor device, comprising:

a substrate comprising a source region and a drain region;

a bit storing element formed on the substrate;

a memory gate structure;

a first insulating layer formed on the substrate;

a second insulating layer formed on the substrate; and

a select gate structure formed on the first insulating layer such that the select gate structure and the second insulating layer are formed on a sidewall of the memory gate structure,

wherein the second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure, and wherein the second insulating layer comprises a plurality of insulating layers, wherein one insulating layer of the plurality of insulating layers is separated from the bit storing element by another insulating layer of the plurality of insulating layers.

12. The semiconductor device of claim 11 , wherein the second insulating layer is formed on the sidewall of the memory gate structure and the memory gate structure is formed above the bit storing element.

13. The semiconductor device of claim 11 , wherein at least a portion of the first insulating layer was formed on the substrate at a same time as at least a portion of the second insulating layer was formed on the substrate.

14. The semiconductor device of claim 11 , wherein the first insulating layer and the second insulating layer form a continuous shape.