Thin film transistor substrate and display device using the same
A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.
1. A thin film transistor substrate comprising:
a first thin film transistor on a substrate and including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode and a first drain electrode;
a second thin film transistor separated from the first thin film transistor and including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode that are disposed on a layer covering the first gate electrode; and
a plurality of storage capacitors separated from the first and second thin film transistors, the plurality of storage capacitors each including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, an intermediate insulating layer on the first dummy gate electrode, a second dummy gate electrode on the intermediate insulating layer, a second gate insulating layer on the second dummy gate electrode, a first dummy source-drain electrode on the second gate insulating layer, a passivation layer on the first dummy source-drain electrode, and a dummy pixel electrode on the passivation layer.
2. The thin film transistor substrate of claim 1 , wherein the dummy pixel electrode is positioned on a planarization layer covering the passivation layer.
3. The thin film transistor substrate of claim 1 , wherein the intermediate insulating layer includes a first intermediate insulating layer formed of silicon nitride and a second intermediate insulating layer formed on the first intermediate insulating layer using silicon oxide.
4. The thin film transistor substrate of claim 1 , wherein the first dummy source-drain electrode is connected to the first dummy gate electrode through a contact hole,
wherein the second dummy gate electrode is connected to a second dummy source-drain electrode separated from the first dummy source-drain electrode through a contact hole,
wherein the second dummy source-drain electrode is connected to the first dummy semiconductor layer through a contact hole, and
wherein the dummy pixel electrode is connected to the second dummy source-drain electrode through a contact hole.
5. The thin film transistor substrate of claim 1 , wherein the first dummy source-drain electrode is connected to the first dummy semiconductor layer through a contact hole,
wherein a second dummy source-drain electrode positioned on the same stratum as the first dummy source-drain electrode is connected to the first dummy gate electrode through a contact hole, and
wherein the dummy pixel electrode is connected to the second dummy source-drain electrode through a contact hole.
6. The thin film transistor substrate of claim 1 , wherein the first source electrode includes a first lower source electrode positioned on the intermediate insulating layer and a first upper source electrode positioned on the second gate insulating layer covering the first lower source electrode, and
wherein the first drain electrode includes a first lower drain electrode positioned on the intermediate insulating layer and a first upper drain electrode positioned on the second gate insulating layer covering the first lower drain electrode.
7. The thin film transistor substrate of claim 1 , wherein the polycrystalline semiconductor layer, the first gate electrode, and the first source and drain electrodes are sequentially stacked on the substrate.
8. The thin film transistor substrate of claim 1 , wherein the layer covering the first gate electrode is the polycrystalline semiconductor layer of the first thin film transistor.
9. An organic light emitting diode display comprising a thin film transistor substrate according to claim 1 .
10. A liquid crystal display comprising a thin film transistor substrate according to claim 1 .