Power devices, structures, components, and methods using lateral drift, fixed net charge, and shield
Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
1. A method of operating a semiconductor device, comprising:
in the ON state, applying a voltage to an insulated gate to thereby invert a portion of a second-conductivity-type body region interposed between a first-conductivity-type source region and a second-conductivity-type drift region to thereby form a channel, and thereby allow passage of majority carriers from said source region through said channel, and through a portion of said drift region which has been inverted by immobile permanent net electrostatic charge, to a first-conductivity-type drain region; and
in the OFF state, at least partially balancing the space charge of depleted portions of said drift region with said immobile permanent net electrostatic charge; and
reducing capacitive coupling by a shield electrode which is interposed between said gate electrode and said drain.
2. The method of claim 1 , wherein said drift region is a well.
3. The method of claim 1 , wherein, in the ON state, said channel and said drift region both carry current flow in a predominantly horizontal direction.
4. The method of claim 1 , wherein, in the ON state, said channel carries a flow of majority carriers in a plane which is predominantly normal to the plane of flow of majority carriers in said drift region.
5. The method of claim 1 , wherein, in the ON state, said channel carries a flow of majority carriers in a plane which is predominantly normal to the surface of a semiconductor die, and said drift region carries a flow of majority carriers which is predominantly parallel to said surface.
6. The method of claim 1 , wherein said gate electrode and said shield electrode both lie in the same plane of metallization.
7. The method of claim 1 , wherein said shield electrode is connected to a fixed potential, but said gate electrode is not.