Mapping table loading method, memory control circuit unit and memory storage apparatus

1. A mapping table loading method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores a plurality of logical address-physical address mapping tables, and each of the logical address-physical address mapping tables has a plurality of sub-logical address-physical address mapping tables, the mapping table loading method comprising:

receiving a first command, wherein the first command corresponds to data stored in a first logical address;

loading a first sub-logical address-physical address mapping table among the sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into a buffer memory if an operating mode corresponding to the rewritable non-volatile memory module is a first operating mode, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address; and

loading a first logical address-physical address mapping table among the logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory if the operating mode corresponding to the rewritable non-volatile memory module is a second operating mode, wherein the first logical address-physical address mapping table records the mapping information corresponding to the first logical address,

wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

2. The mapping table loading method of claim 1 , wherein before the step of receiving the first command, the mapping table loading method further comprises:

executing a second command according to a second sub-logical address-physical address mapping table;

determining the operating mode of the rewritable non-volatile memory module as the first operating mode if the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table; and

determining the operating mode of the rewritable non-volatile memory module as the second operating mode if the second sub-logical address-physical address mapping table is identical to the first sub-logical address-physical address mapping table.

3. The mapping table loading method of claim 2 , wherein when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, the mapping table loading method further comprises:

determining the operating mode of the rewritable non-volatile memory module as the second operating mode if the first logical address-physical address mapping table includes the second sub-logical address-physical address mapping table.

4. The mapping table loading method of claim 1 , wherein before the step of receiving the first command, the mapping table loading method further comprises:

executing a third command according to a second logical address-physical address mapping table; and

determining the operating mode of the rewritable non-volatile memory module as the first operating mode if the second logical address-physical address mapping table is different from the first logical address-physical address mapping table.

5. The mapping table loading method of claim 1 , wherein when the operating mode of the rewritable non-volatile memory module is the first operating mode, the mapping table loading method further comprises:

executing the first command according to the first sub-logical address-physical address mapping table;

erasing the first sub-logical address-physical address mapping table; and

recording a usage history of the first sub-logical address-physical address mapping table into a management table.

6. The mapping table loading method of claim 1 , wherein the operating mode of the rewritable non-volatile memory module is preset as the first operating mode each time after power-on.

7. The mapping table loading method of claim 1 , wherein the first operating mode comprises a random read operating mode, a random write operating mode or an operating mode for selecting recycle blocks in a garbage collection procedure.

8. The mapping table loading method of claim 1 , wherein the second operating mode comprises a sequential read operating mode, a sequential write operating mode, an operating mode for writing target blocks in a garbage collection procedure or a flush operating mode.

9. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising:

a host interface configured to couple to a host system;

a memory interface configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores a plurality of logical address-physical address mapping tables, and each of the logical address-physical address mapping tables has a plurality of sub-logical address-physical address mapping tables;

a buffer memory; and

a memory management circuit coupled to the host interface, the memory interface and the buffer memory,

the memory management circuit is configured to receive a first command, wherein the first command corresponds to data stored in a first logical address;

the memory management circuit is further configured to load a first sub-logical address-physical address mapping table among the sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory if an operating mode corresponding to the rewritable non-volatile memory module is a first operating mode, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address,

the memory management circuit is further configured to load a first logical address-physical address mapping table among the logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory if the operating mode corresponding to the rewritable non-volatile memory module is a second operating mode, wherein the first logical address-physical address mapping table records the mapping information corresponding to the first logical address,

wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

10. The memory control circuit unit of claim 9 , wherein before the operation of receiving the first command,

the memory management circuit is further configured to execute a second command according to a second sub-logical address-physical address mapping table,

the memory management circuit is further configured to determine the operating mode of the rewritable non-volatile memory module as the first operating mode if the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, and

the memory management circuit is further configured to determine the operating mode of the rewritable non-volatile memory module as the second operating mode if the second sub-logical address-physical address mapping table is identical to the first sub-logical address-physical address mapping table.

11. The memory control circuit unit of claim 10 , wherein when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table,

the memory management circuit is further configured to determine the operating mode of the rewritable non-volatile memory module as the second operating mode if the first logical address-physical address mapping table includes the second sub-logical address-physical address mapping table.

12. The memory control circuit unit of claim 9 , wherein before the operation of receiving the first command,

the memory management circuit is further configured to execute a third command according to a second logical address-physical address mapping table, and

the memory management circuit is further configured to determine the operating mode of the rewritable non-volatile memory module as the first operating mode if the second logical address-physical address mapping table is different from the first logical address-physical address mapping table.

13. The memory control circuit unit of claim 9 , wherein when the operating mode of the rewritable non-volatile memory module is the first operating mode,

the memory management circuit is further configured to execute the first command according to the first sub-logical address-physical address mapping table,

the memory management circuit is further configured to erase the first sub-logical address-physical address mapping table, and

the memory management circuit is further configured to record a usage history of the first sub-logical address-physical address mapping table into a management table.

14. The memory control circuit unit of claim 9 , wherein the operating mode of the rewritable non-volatile memory module is preset as the first operating mode each time after power-on.

15. The memory control circuit unit of claim 9 , wherein the first operating mode comprises a random read operating mode, a random write operating mode or an operating mode for selecting recycle blocks in a garbage collection procedure.

16. The memory control circuit unit of claim 9 , wherein the second operating mode comprises a sequential read operating mode, a sequential write operating mode, an operating mode for writing target blocks in a garbage collection procedure or a flush operating mode.

17. A memory storage apparatus, comprising:

a connection interface unit configured to couple to a host system;

a rewritable non-volatile memory module configured to store a plurality of logical address-physical address mapping tables, wherein each of the logical address-physical address mapping tables has a plurality of sub-logical address-physical address mapping tables; and

a memory control circuit unit comprising a buffer memory, wherein the memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to receive a first command, wherein the first command corresponds to data stored in a first logical address;

the memory control circuit unit is further configured to load a first sub-logical address-physical address mapping table among the sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory if an operating mode corresponding to the rewritable non-volatile memory module is a first operating mode, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address,

the memory control circuit unit is further configured to load a first logical address-physical address mapping table among the logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory if the operating mode corresponding to the rewritable non-volatile memory module is a second operating mode, wherein the first logical address-physical address mapping table records the mapping information corresponding to the first logical address,

wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

18. The memory storage apparatus of claim 17 , wherein before the operation of receiving the first command,

the memory control circuit unit is further configured to execute a second command according to a second sub-logical address-physical address mapping table,

the memory control circuit unit is further configured to determine the operating mode of the rewritable non-volatile memory module as the first operating mode if the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, and

the memory control circuit unit is further configured to determine the operating mode of the rewritable non-volatile memory module as the second operating mode if the second sub-logical address-physical address mapping table is identical to the first sub-logical address-physical address mapping table.

19. The memory storage apparatus of claim 18 , wherein when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table,

the memory control circuit unit is further configured to determine the operating mode of the rewritable non-volatile memory module as the second operating mode if the first logical address-physical address mapping table includes the second sub-logical address-physical address mapping table.

20. The memory storage apparatus of claim 17 , wherein before the operation of receiving the first command,

the memory control circuit unit is further configured to execute a third command according to a second logical address-physical address mapping table,

the memory control circuit unit is further configured to determine the operating mode of the rewritable non-volatile memory module as the first operating mode if the second logical address-physical address mapping table is different from the first logical address-physical address mapping table.

21. The memory storage apparatus of claim 17 , wherein when the operating mode of the rewritable non-volatile memory module is the first operating mode,

the memory control circuit unit is further configured to execute the first command according to the first sub-logical address-physical address mapping table,

the memory control circuit unit is further configured to erase the first sub-logical address-physical address mapping table, and

the memory control circuit unit is further configured to record a usage history of the first sub-logical address-physical address mapping table into a management table.

22. The memory storage apparatus of claim 17 , wherein the operating mode of the rewritable non-volatile memory module is preset as the first operating mode each time after power-on.

23. The memory storage apparatus of claim 17 , wherein the first operating mode comprises a random read operating mode, a random write operating mode or an operating mode for selecting recycle blocks in a garbage collection procedure.

24. The memory storage apparatus of claim 17 , wherein the second operating mode comprises a sequential read operating mode, a sequential write operating mode, an operating mode for writing target blocks in a garbage collection procedure or a flush operating mode.