Apparatus and method for cyclic redundancy check

1. An apparatus for cyclic redundancy check (CRC) operating with a polynomial having n degrees, the apparatus comprising:

a multiplicity of sub-block CRC parts configured to receive in parallel a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks, and configured to perform CRC in parallel; and

a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field,

wherein each sub-block CRC part comprises:

a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field; and

a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field.

2. The apparatus of claim 1 , wherein orders of sub-blocks of the transport block increase toward a most significant bit from a least significant bit,

wherein, if an order of a sub-block is P and a size of the sub-block is N, the number of bit of a sub-block weight code of the sub-block is (P−1)×N+1, a most significant bit of the sub-block weight code is 1, and the rest bits of the sub-block weight code are 0.

3. The apparatus of claim 1 , if a size of a sub-block is N and an order of a corresponding sub-block of the transport block is P, further comprising:

a storage unit configured to store a reference weight CRC code that is preliminarily obtained through CRC calculation of a code that has the number of bits of N+1, a most significant bit of 1, and the rest bits of 0; and

a first code generating part configured to generate a first code from a corresponding sub-block by multiplying the reference weight CRC codes, which are counted by subtracting 1 from P, in the Galois field.

4. The apparatus of claim 1 , wherein, provided a size of the bit sequence is S, if S=1, the linear feedback shift register is a 1-bit serial linear feedback shift register that calculates 1 bit per one cycle, and if S>1, the linear feedback shift register is an S-bit parallel linear feedback shift register that calculates S bits per one cycle.

5. A method for cyclic redundancy check (CRC) operating with a polynomial having n degrees, the method comprising:

receiving, in parallel, a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks;

generating a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in a Galois field;

outputting a second code by adding the weight bit sequence to n-numbered registers, which are included a linear feedback shift register, in the Galois field; and

adding the second codes to the multiplicity of sub-blocks in the Galois field.

6. The method of claim 5 , wherein the generating of the weight bit sequence further comprises:

invoking a reference weight CRC code, which is obtained by CRC-calculating of a code that has the number of bits of N+1, a most significant bit of 1, and the rest bits of 0, from a storage unit; and

generating a first code of a corresponding sub-block by multiplying the reference the weight CRC codes, which are counted by subtracting 1 from P, in the Galois field,

wherein the N is a size of a corresponding sub-block, the P is an order of a corresponding sub-block of the transport block, and orders of sub-blocks of the transport block increase toward the most significant bit from a least significant bit.

7. A computer-readable storage medium configured to store a computer program that executes the method for CRC according to claim 5 .