IP Library Granted Patent US 9,490,755
Granted Patent B2
US 9,490,755 · App. 15/184,910 · Granted Nov 8, 2016

Phase shift and attenuation circuits for use with multiple-path amplifiers

Inventors: Abdulrhman M. S. Ahmed (Gilbert, AZ); Mario M. Bokatius (Chandler, AZ); Paul R. Hart (Phoenix, AZ); Joseph Staudinger (Gilbert, AZ); Richard E. Sweeney (Chandler, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H03F1/0288G06F13/4282H03F3/19H03F3/211H04L7/0079H04L27/22H03F2200/451
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Quick Facts
Patent No.
US 9,490,755
App. No.
15/184,910
Granted
Nov 8, 2016
Kind
B2
Abstract

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Claims (32)

1. An adjustable power splitter circuit comprising:

a power divider with a power divider input, a first power divider output, and a second power divider output, wherein the power divider is configured to divide a first radio frequency (RF) input signal received at the power divider input into first and second divided RF signals provided at the first and second power divider outputs;

a first circuit comprising a first input coupled to the first power divider output and configured to receive the first divided RF signal, a first output configured to provide a first RF output signal, and a first adjustable phase shifter circuit and a first adjustable attenuator circuit series coupled between the first input and the first output, wherein the first adjustable phase shifter circuit and the first adjustable attenuator circuit are separate circuits, the first adjustable phase shifter circuit is configured to apply a first phase shift to the first divided RF signal, and the first adjustable attenuator circuit is configured to apply a first attenuation to the first divided RF signal;

a second circuit in parallel with the first circuit, the second circuit comprising a second input coupled to the second power divider output and configured to receive the second divided RF signal, a second output configured to provide a second RF output signal, and a second adjustable phase shifter circuit coupled between the second input and the second output, wherein the second adjustable phase shifter circuit is configured to apply a second phase shift to the second divided RF signal; and

a controller configured to receive data indicating the first and second phase shifts and the first attenuation, and to control, based on the data, application of the first and second phase shifts by the first and second adjustable phase shifter circuits, and application of the first attenuation by the first adjustable attenuator circuit.

2. The circuit of claim 1 , wherein, prior to application of the first phase shift, the first attenuation, and the second phase shift, the adjustable power splitter is configured to give a ninety degree phase shift between the two RF signals provided to the first circuit and the second circuit.

3. The circuit of claim 1 , wherein the first adjustable attenuator circuit and the first adjustable phase shifter circuit are separately controllable, and wherein each of the first adjustable attenuator circuit and the first adjustable phase shifter circuit is digitally controlled and has a plurality of states.

4. The circuit of claim 1 , wherein the second circuit further comprises a second attenuator circuit coupled in series with the second adjustable phase shifter circuit.

5. The circuit of claim 4 , wherein the second attenuator circuit is an adjustable attenuator.

6. The circuit of claim 5 , wherein the second attenuator circuit is digitally controlled and has a plurality of states.

7. The circuit of claim 4 , wherein the second attenuator circuit is configured to apply zero decibels of attenuation.

8. The circuit of claim 1 , further comprising:

a third series circuit in parallel with the first and second series circuits, the third series circuit comprising a third input coupled to a third power divider output, a third output, and a third adjustable phase shifter circuit and a third attenuator circuit series coupled between the third input and the third output.

9. The circuit of claim 8 , wherein the power divider further comprises:

the third power divider output, wherein the power divider is configured to divide the RF signal received at the power divider input into three RF signals provided at the first, second, and third power divider outputs.

10. The circuit of claim 1 wherein the first adjustable phase shifter circuit and the second adjustable phase shifter circuit are digitally controlled and each has a plurality of states.

11. The circuit of claim 1 , further comprising:

an interface, wherein the controller is configured to receive the data indicating the phase shifts to be applied via the interface.

12. The circuit of claim 11 , wherein the interface is selected from a serial interface and a serial peripheral interface.

13. The circuit of claim 11 , wherein the data includes a multiple-bit value that uniquely specifies one of multiple phase shifted states for the first and second adjustable phase shifter circuits and one of multiple attenuation states for the first adjustable attenuator circuit.

14. A circuit for use with an amplifier that includes multiple amplifier paths, the circuit comprising:

a power divider with a power divider input, a first power divider output, and a second power divider output, wherein the power divider is configured to divide a radio frequency (RF) signal received at the power divider input into two RF signals provided at the first and second power divider outputs;

a first circuit coupled to the first power divider output, the first circuit comprising a first input coupled to a first power divider output, a first output configured to be coupled to a first amplifier input, and a first adjustable phase shifter circuit and a first attenuator circuit series coupled between the first input and the first output, wherein the first adjustable phase shifter circuit and the first adjustable attenuator circuit are separate circuits; and

a second circuit in parallel with the first circuit and coupled to the second power divider output, the second circuit comprising a second input coupled to a second power divider output, a second output configured to be coupled to a second amplifier input, and a second adjustable phase shifter circuit coupled between the second input and the second output.

15. The circuit of claim 14 , wherein the first adjustable phase shifter circuit and the first adjustable attenuator circuit are separately controllable circuits.

16. The circuit of claim 14 , further comprising:

a controller configured to receive data indicating the first phase shift, data indicating the second phase shift, and data indicating the first attenuation, and to control, based on the data, application of the first and second phase shifts by the first and second adjustable phase shifter circuits, and application of the first attenuation by the first adjustable attenuator circuit.

17. The circuit of claim 16 , wherein the controller separately controls the first adjustable phase shifter circuit and the first adjustable attenuator circuit.

18. The circuit of claim 16 , further comprising:

a digital data interface, wherein the controller is configured to receive the data indicating the first and second phase shifts and the data indicating the first attenuation via the interface.

19. The circuit of claim 14 , wherein, prior to application of the first phase shift, the first attenuation, and the second phase shift, the circuit is configured to give a ninety degree phase shift between the two RF signals provided to the first circuit and the second circuit.

20. The circuit of claim 14 , wherein the amplifier is a Doherty power amplifier comprising a main amplifier path and a peaking amplifier path, and wherein the first amplifier input is coupled to the main amplifier path, and the second amplifier input is coupled to the peaking amplifier path.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2016
From: AHMED, ABDULRHMAN M.S.; BOKATIUS, MARIO M.; HART, PAUL R.; STAUDINGER, JOSEPH; SWEENEY, RICHARD E.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 038937/0661 →
Continuity (5)
Continuation 14728196 · Jun 2, 2015
Continuation 14287139 · May 26, 2014
Continuation 13959254 · Aug 5, 2013
Continuation 13360473 · Jan 27, 2012
Related Publication 20160294330A1 · Oct 6, 2016