IP Library Granted Patent US 9,947,627
Granted Patent B2
US 9,947,627 · App. 15/186,937 · Granted Apr 17, 2018

Guard ring structure and method for forming the same

Inventors: Chiyuan Lu (San Jose, CA); Chien-Chih Lin (Hsinchu, TW); Cheng-Chou Hung (Hukou Township, Hsinchu County, TW); Yu-Hua Huang (Hsinchu, TW)
Assignee: MEDIATEK SINGAPORE PTE. LTD.
H01L23/564H01L21/761H01L21/76802H01L23/498H01L23/585H01L29/0623H01L27/0814H01L29/872H01L2924/00H01L2924/0002
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Quick Facts
Patent No.
US 9,947,627
App. No.
15/186,937
Granted
Apr 17, 2018
Kind
B2
Abstract

A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.

Claims (15)

1. A guard ring structure, comprising

a semiconductor substrate with a circuit region encircled by a first ring and a second ring, and at least one of the first and second ring comprises:

a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and

an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions, wherein the plurality of separated doping regions are electrically connected to each other via the interconnect element.

2. The guard ring structure as claimed in claim 1 , further comprising an isolation region formed over the semiconductor substrate and between and adjacent to the doping regions.

3. The guard ring structure as claimed in claim 1 , wherein the interconnect element comprises a plurality of levels of conductive via and conductive line that are alternately stacked over the semiconductor substrate.

4. The guard ring structure as claimed in claim 3 , wherein the conductive via and conductive line comprise aluminum or copper.

5. The guard ring structure as claimed in claim 1 , wherein the substrate has a first dopant type, and the doping regions have a second dopant type opposite to the first dopant type, thereby forming P-N junction or N-P junction between the substrate and the doping regions.

6. The guard ring structure as claimed in claim 1 , wherein the at least one of the first and second ring further comprises:

another doping region embedded in a portion of the semiconductor substrate and formed below the plurality of separated doping regions, wherein P-N junction or N-P junction is formed between the another doping region and the plurality of separated doping regions, or is formed between the another doping region and the substrate.

7. The guard ring structure as claimed in claim 6 , wherein the plurality of separated doping regions are formed in a top portion of the semiconductor substrate, overlying the another doping region and have a first dopant type, the another doping region has a second dopant type opposite to the first dopant type, and the substrate has the first dopant type, thereby P-N junction or N-P junction is formed between the another doping region and the plurality of separated doping regions, and is formed between the another doping region and the substrate.

8. The guard ring structure as claimed in claim 7 , wherein the first dopant type is p-type, and the second dopant type is n-type.

9. The guard ring structure as claimed in claim 6 , wherein the another doping region comprises a resistivity lower than that of the semiconductor substrate.

10. The guard ring structure as claimed in claim 1 , wherein the plurality of separated doping regions comprise a resistivity lower than that of the semiconductor substrate.

11. The guard ring structure as claimed in claim 6 , further comprising a well region embedded in the semiconductor substrate and disposed adjacent to the another doping region.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 060646 FRAME: 0916. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 23, 2022
From: FORTIETH FLOOR, LLC
To: HAMILCAR BARCA IP LLC
Reel/Frame 061301/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: FORTIETH FLOOR, LLC
To: HANNIBAL BARCA IP LLC
Reel/Frame 060646/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: MEDIATEK SINGAPORE PTE LTD.
To: FORTIETH FLOOR LLC
Reel/Frame 058342/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2016
From: LU, CHIYUAN; LIN, CHIEN-CHIH; HUNG, CHENG-CHOU; HUANG, YU-HUA
To: MEDIATEK SINGAPORE PTE. LTD.
Reel/Frame 038958/0373 →
Continuity (3)
Continuation 14020367 · Sep 6, 2013
Provisional Application 61698443 · Sep 7, 2012
Related Publication 20160300801A1 · Oct 13, 2016