Semiconductor die singulation methods

1. A method of singulating a plurality of die, the method comprising: providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness; etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die; and adding memory data to one or more of the plurality of die after etching the plurality of trenches; mounting the first side of the semiconductor wafer to a tape after adding memory data to one or more of the plurality of die; thinning a second side of the semiconductor wafer; exposing the plurality of trenches while thinning the second side; and singulating the plurality of die through exposing the plurality of trenches.

2. The method of claim 1 , further comprising picking the plurality of die from the tape.

3. The method of claim 1 , further comprising flipping the plurality of die to transfer them from the tape to a picking tape.

4. The method of claim 1 , wherein etching the plurality of trenches further comprises defining a pattern of the plurality of trenches using one of passivation material, metal material, photolithographic masking, temporary film, shadow masking, and any combination thereof.

5. The method of claim 1 , wherein the semiconductor wafer comprises silicon and etching the plurality of trenches further comprises using a Bosch deep reactive ion etch (DRIE) process.

6. The method of claim 1 , further comprising one of the following after etching the plurality of trenches:

forming a plurality of bumps on the plurality of die;

testing one or more of the plurality of die;

probing one or more of the plurality of die;

forming a solderable surface on a surface of one or more of the plurality of die; and

any combination thereof.

7. A method of singulating a plurality of die, the method comprising:

providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness;

etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die;

mounting the first side of the semiconductor wafer to a back grinding tape;

thinning a second side of the semiconductor wafer to a predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches;

demounting the first side of the semiconductor wafer from the back grinding tape;

mounting the first side of the semiconductor wafer to a picking tape;

one of etching and grinding the second side of the semiconductor wafer to expose the plurality of trenches; and

singulating the plurality of die through exposing the plurality of trenches.

8. The method of claim 7 , wherein etching the plurality of trenches further comprises defining a pattern of the plurality of trenches using one of passivation material, metal material, photolithographic masking, temporary film, shadow masking, and any combination thereof.

9. The method of claim 7 , wherein the semiconductor wafer comprises silicon and etching the plurality of trenches further comprises using a Bosch deep reactive ion etch (DRIE) process.

10. The method of claim 7 , further comprising one of the following after etching the plurality of trenches:

forming a plurality of bumps on the plurality of die;

testing one or more of the plurality of die;

probing one or more of the plurality of die;

adding memory data to one or more of the plurality of die;

forming a solderable surface on a surface of one or more of the plurality of die; and

any combination thereof.

11. The method of claim 7 , wherein etching the second side of the semiconductor wafer to expose the plurality of trenches further comprises etching using one of plasma etching, wet etching, and any combination thereof.

12. The method of claim 7 , wherein thinning the second side of the semiconductor wafer to the predetermined distance further comprises using a Taiko grinding process.

13. A method of singulating a plurality of die, the method comprising:

providing a semiconductor wafer comprising a plurality of die located on a first side of the semiconductor wafer, the plurality of die comprising a desired thickness and an under bump metal layer;

etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer, the plurality of trenches located adjacent a perimeter of the plurality of die and a depth of the plurality of trenches being greater than the desired thickness of the plurality of die;

forming one or more bumps on the under bump metal layer of one or more of the plurality of die;

mounting the first side of the semiconductor wafer to a back grinding tape;

thinning a second side of the semiconductor wafer to a predetermined distance between the second side of the semiconductor wafer and the depth of the plurality of trenches;

demounting the first side of the semiconductor wafer from the back grinding tape;

mounting the first side of the semiconductor wafer to a picking tape;

one of etching and grinding the second side of the semiconductor wafer to expose the plurality of trenches; and

singulating the plurality of die through exposing the plurality of trenches.

14. The method of claim 13 , wherein etching the second side of the semiconductor wafer to expose the plurality of trenches further comprises etching using one of plasma etching, wet etching, and any combination thereof.

15. The method of claim 13 , wherein thinning the second side of the semiconductor wafer to the predetermined distance further comprises using a Taiko grinding process.