IP Library Granted Patent US 9,524,953
Granted Patent B2
US 9,524,953 · App. 15/191,774 · Granted Dec 20, 2016

Electronic device

Inventors: Yoichiro Kurita (Tokyo, JP); Masaya Kawano (Tokyo, JP); Koji Soejima (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L25/0657H01L25/50H01L2225/06513H01L2225/06544H01L2225/06555H01L2225/06582
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Quick Facts
Patent No.
US 9,524,953
App. No.
15/191,774
Granted
Dec 20, 2016
Kind
B2
Abstract

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Claims (8)

1. A electronic device comprising:

a substrate having a first main surface, a second main surface opposite the first main surface and a plurality of wirings;

a first semiconductor chip arranged above the first main surface and having a first obverse surface, a CPU circuit and a plurality of bumps formed on the first obverse surface;

a first memory chip having a first group of electrodes;

a second memory chip having a second group of electrodes and through electrodes penetrating the second memory chip in a thickness direction of the second memory chip, the through electrodes being electrically connected to the second group of electrodes; and

the first memory chip stacked on the second memory chip over the substrate such that the first group of electrodes of the first memory chip are electrically connected to the through electrodes of the second memory chip,

wherein the first group of electrodes of the first memory chip, the second groups of electrodes of the second memory chips are arranged in a first predetermined pitch, and

wherein the bumps of the first semiconductor chip, the second groups of electrodes of the second memory chips are electrically connected to the wirings of the substrate.

Assignments (3)
ADDRESS CHANGE Recorded Aug 26, 2016
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 039831/0062 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2016
From: KURITA, YOICHIRO; KAWANO, MASAYA; SOEJIMA, KOJI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 039003/0017 →
CHANGE OF NAME Recorded Jun 24, 2016
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 039003/0152 →
Priority Claims (1)
JP 2006-271154 · Oct 2, 2006 · national
Continuity (6)
Continuation 14606425 · Jan 27, 2015
Continuation 14455336 · Aug 8, 2014
Continuation 14108960 · Dec 17, 2013
Division 13712224 · Dec 12, 2012
Division 11865745 · Oct 2, 2007
Related Publication 20160307875A1 · Oct 20, 2016