Complementary metal-oxide-semiconductor depth sensor element
A complementary metal-oxide-semiconductor depth sensor element comprises a photogate formed in a photosensitive area on a substrate. A first transfer gate and a second transfer gate are formed respectively on two sides of the photogate in intervals. A first floating doped area and a second floating doped area are formed respectively on the outer sides of the first transfer gate and the second transfer gate. The first and second floating doped regions have dopants of a first polarity and the semiconductor area has dopants of a second polarity opposite to the first polarity. Since the photogate and at least parts of the first and second transfer gates connect to the same semiconductor area and no other dopants of polarity opposite to the second polarity. Therefore, the majority carriers from the photogate excited by lights drift, but not diffuse, to transfer to the first and second transfer gates.
1. A depth sensor element comprising:
a substrate comprising a photosensitive region;
a semiconductor region formed on the substrate;
a photogate formed on the semiconductor region, corresponding to the photosensitive region and having a first side and a second side;
a first transfer gate formed on the semiconductor region and having
a first side; and
a second side adjacent to the first side of the photogate;
a first gap formed between the second side of the first transfer gate and the first side of the photogate;
a second transfer gate formed on the semiconductor region and having
a first side adjacent to the second side of the photogate; and
a second side;
a second gap formed between the first side of the second transfer gate and the second side of the photogate;
a first floating doped region formed in the semiconductor region, connected to the first side of the first transfer gate and being as a first transmitting node; and
a second floating doped region formed in the semiconductor region, connected to the second side of the second transfer gate and being as a second transmitting node;
wherein the photogate, at least a part of the first transfer gate, at least a part of the second transfer gate connect to the same semiconductor region, and the first and second floating doped regions have dopants of a first polarity and the semiconductor region has dopants of a second polarity opposite to the first polarity.
2. The depth sensor element as claimed in claim 1 further comprising:
a first reset transistor comprising a first gate and a first drain/source doped region, wherein two sides of the first gate are respectively connected to the first floating doped region and the first drain/source doped region;
a second reset transistor comprising a second gate and a second drain/source doped region, wherein two sides of the second gate are respectively connected to the second floating doped region and the second drain/source doped region;
a first trench isolating region, wherein two sides of the first drain/source doped region respectively correspond to the first gate and the first trench isolating region;
a second trench isolating region, wherein two sides of the second drain/source doped region respectively correspond to the second gate and the second trench isolating region;
wherein the first and second drain/source doped regions have dopants of the first polarity and the semiconductor region has dopants of the second polarity opposite to the first polarity.
3. The depth sensor element as claimed in claim 2 , wherein an epitaxy is formed on the substrate and the semiconductor region is formed in the epitaxy.
4. The depth sensor element as claimed in claim 2 , wherein
the semiconductor region is an epitaxy;
a doped well is formed in the epitaxy and corresponds to the first and second gates; and
the first and second drain/source doped regions and the first trench isolating region are formed in the doped well.
5. The depth sensor element as claimed in claim 3 , wherein the substrate is a p-type substrate;
the epitaxy is a p-type epitaxy;
the first and second floating doped regions are n-type doped regions; and
the first and second drain/source doped regions are n-type doped regions.
6. The depth sensor element as claimed in claim 4 , wherein
the substrate is a p-type substrate;
the epitaxy is a p-type epitaxy;
the doped well is a p-type doped well;
the first and second floating doped regions are n-type doped regions; and
the first and second drain/source doped regions are n-type doped regions.
7. The depth sensor element as claimed in claim 2 further comprising:
two amplifier transistors, and each amplifier transistor having a gate, and the two gates of the amplifier transistors respectively coupled to the first and second floating doped regions; and
two selection transistors, and each selection transistor coupling to a corresponding amplifier transistor, a column bit line and a row selection line.
8. The depth sensor element as claimed in claim 3 further comprising:
two amplifier transistors, and each amplifier transistor having a gate, and the two gates of the amplifier transistors respectively coupled to the first and second floating doped regions; and
two selection transistors, and each selection transistor coupling to a corresponding amplifier transistor, a column bit line and a row selection line.
9. The depth sensor element as claimed in claim 4 further comprising:
two amplifier transistors, and each amplifier transistor having a gate, and the two gates of the amplifier transistors respectively coupled to the first and second floating doped regions; and
two selection transistors, and each selection transistor coupling to a corresponding amplifier transistor, a column bit line and a row selection line.
10. The depth sensor element as claimed in claim 5 further comprising:
two amplifier transistors, and each amplifier transistor having a gate, and the two gates of the amplifier transistors respectively coupled to the first and second floating doped regions; and
two selection transistors, and each selection transistor coupling to a corresponding amplifier transistor, a column bit line and a row selection line.
11. The depth sensor element as claimed in claim 6 further comprising:
two amplifier transistors, and each amplifier transistor having a gate, and the two gates of the amplifier transistors respectively coupled to the first and second floating doped regions; and
two selection transistors, and each selection transistor coupling to a corresponding amplifier transistor, a column bit line and a row selection line.
12. The depth sensor element as claimed in claim 1 , wherein
the photogate has multiple sub-photogates arranged in parallel, wherein
at a first time phase, from the first transfer gate to the second transfer gate, the first transfer gate and the sub-photogates are supplied descending voltages; and
at a second time phase, form the second transfer gate to the first transfer gate, the second transfer gate and the sub-photogates are supplied descending voltages.
13. The depth sensor element as claimed in claim 12 , wherein the sub-photogates have the same area.
14. The depth sensor element as claimed in claim 12 , wherein the sub-photogates have different areas.
15. The depth sensor element as claimed in claim 2 , wherein
the photogate has multiple sub-photogates arranged in parallel, wherein
at a first time phase, from the first transfer gate to the second transfer gate, the first transfer gate and the sub-photogates are supplied descending voltages; and
at a second time phase, form the second transfer gate to the first transfer gate, the second transfer gate and the sub-photogates are supplied descending voltages.
16. The depth sensor element as claimed in claim 15 , wherein the sub-photogates have the same area.
17. The depth sensor element as claimed in claim 15 , wherein the sub-photogates have different areas.
18. The depth sensor element as claimed in claim 1 , wherein the first and second gap is between 0.01 micrometer to 0.4 micrometer.
19. A sensing method of a depth sensor element, wherein the depth sensor element has a photogate, a first transfer gate and a second transfer gate, and the first and second transfer gates are formed on two sides of the photogate, and the photogate has multiple sub-photogates, the method comprises acts of:
at a first time phase, from the first transfer gate to the second transfer gate, the first transfer gate and the sub-photogates are supplied descending voltages; and
at a second time phase, form the second transfer gate to the first transfer gate, the second transfer gate and the sub-photogates are supplied descending voltages.