Staircase forward error correction coding
In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B i , a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block B i in the sequence are computed. The coding symbols are computed such that, for each symbol block B i that has a preceding symbol block B i−1 and a subsequent symbol block B i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B i−1 , concatenated with the data symbols and the coding symbols along the other dimension in the symbol B i , form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol B i , concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B i+1 , form a codeword of the FEC component code. Thus, each row in [B i−1 T B i ] and each column in [ B i B i + 1 T ] , for example, is a valid codeword.
1. An apparatus comprising:
a mapper to receive a stream of data symbols from a transport network and to map the stream of data symbols among data symbol positions in a sequence of two-dimensional symbol blocks B i , i a positive integer, each of the symbol blocks comprising data symbol positions and coding symbol positions; and
a Forward Error Correction (FEC) encoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the mapper, to process coding symbols for the coding symbol positions in each symbol block in the sequence, the coding symbols being processed such that, for each symbol block B i that has a preceding symbol block B i−1 and a subsequent symbol block B i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B i−1 , concatenated with symbols at symbol positions along the other dimension in the symbol block B i , form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block B i , concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block B i+1 , form a codeword of the FEC component code,
wherein each symbol block comprises an n row by m column array of symbols, m, n≥1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block B i based on D i−1 and B i , where D i−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of B i−1 .
2. The apparatus of claim 1 , wherein the mapper maps the stream of data symbols to the symbol positions from one or more Optical channel Transport Unit (OTUk) frames.
3. The apparatus of claim 1 , wherein the predetermined symbols comprise all zeros.
4. The apparatus of claim 1 , wherein the symbol blocks comprise 512 rows by 510 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (1022, 990) code.
5. The apparatus of claim 4 , wherein the mapping comprises mapping information bits of two Optical channel Transport Unit (OTUk) frames to information symbols in each symbol block B i , i≥1, the method further comprising:
mapping the coding symbols in each symbol block B i−1 , i≥2, to parity bits of the two OTUk frames to which the information symbols in symbol block B i are mapped.
6. The apparatus of claim 1 , wherein the symbol blocks comprise 196 rows by 187 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (383, 353) code.
7. The apparatus of claim 6 , wherein the mapping comprises mapping information bits of one of four rows of an Optical channel Transport Unit (OTUk) frame to information symbols in each symbol block B i , i≥1, and
mapping the coding symbols in each symbol block B i−1 , i≥2, to parity bits of the Optical channel Transport Unit (OTUk) frame to which the information symbols in symbol block B i are mapped.
8. An apparatus that comprises:
an interface to receive a sequence of FEC encoded two-dimensional symbol blocks B i , i a positive integer, each of the received symbol blocks comprising received versions of data symbols at data symbol positions and coding symbols at coding symbol positions, the coding symbols for the coding symbol positions in each symbol block B i in the sequence having been processed at a transmitter of the received symbol blocks such that, for each symbol block B i that has a preceding symbol block B i−1 and a subsequent symbol block B i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B i−1 , concatenated with symbols at symbol positions along the other dimension in the symbol block B i , form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block B i , concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block B i+1 , form a codeword of the FEC component code; and
an FEC decoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the interface, to decode the received FEC encoded symbol blocks,
wherein each symbol block comprises an n row by m column array of symbols, m, n>1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block B i based on D i−1 and B i , where D i−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of B i−1 .