Distributed phase locked loop in hearing instruments
A system, in some embodiments, comprises: an antenna; a receiver, coupled to the antenna, to receive wireless signals from another electronic device; a signal processor (SP) coupled to the receiver; and a phase locked loop (PLL), distributed among the receiver and the SP, to synchronize the frequency of a data sampling clock used by the SP with the frequency of a source clock determined by the receiver.
1. A system, comprising:
a receiver configured to receive wireless signals from an electronic device, the receiver comprising:
receiver logic operable to receive an input signal at a source clock frequency from the electronic device;
a phase detector coupled to the receiver logic and operable to:
receive a data sampling clock; and
compute an error signal indicating a difference between the data sampling clock and the source clock; and
a first communication interface coupled to the phase detector and operable to transmit the input signal; and
a signal processor (SP) coupled to the receiver and comprising:
a second communication interface operable to couple to the first communication interface to communicatively couple the SP to the receiver;
a digitally-controlled oscillator (DCO) coupled to the second communication interface and operable to generate a system clock;
a clock divider coupled to the DCO and the phase detector and operable to generate the data sampling clock based at least partially on the system clock; and
digital signal processing logic coupled to the DCO and the clock divider and operable to process the input signal at a frequency specified by the data sampling clock.
2. The system of claim 1 , wherein said receiver comprises a radio.
3. The system of claim 1 , wherein the receiver is configured to receive wireless signals from an electronic device selected from the group consisting of: a mobile phone; a tablet; a personal computer; a stereo system; and a television.
4. The system of claim 1 , wherein the system clock has a higher frequency than the data sampling clock.
5. The system of claim 1 , further comprising a loop filter coupled between the phase detector and the first communication interface, wherein the loop filter is operable to generate a filtered signal, and wherein the DCO generates an oscillating signal based at least partially on the filtered signal as the system clock.
6. The system of claim 1 , further comprising a loop filter coupled between the second communication interface and the DCO, wherein the loop filter is operable to generate a filtered signal, and wherein the DCO generates an oscillating signal based at least partially on the filtered signal as the system clock.
7. The system of claim 1 , wherein the communication interface is selected from the group consisting of a serial interface and a parallel interface.
8. A signal processor, comprising:
a communication interface operable to receive an input signal from a receiver;
a digitally-controlled oscillator (DCO) coupled to the communication interface and operable to generate a system clock;
a clock divider coupled to the DCO and a phase detector of the receiver and operable to:
generate a data sampling clock based at least partially on the system clock; and
provide the data sampling clock to the receiver coupled to the signal processor; and
digital signal processing logic coupled to the DCO and the clock divider and operable to process the input signal at a frequency specified by the data sampling clock.
9. The signal processor of claim 8 , further comprising a loop filter coupled between the communication interface and the DCO, wherein the loop filter is operable to generate a filtered signal.
10. The signal processor of claim 8 , wherein the communication interface is selected from the group consisting of a serial interface and a parallel interface.
11. The signal processor of claim 8 , wherein the DCO is operable to generate the system clock at least partially based on the input signal, and wherein the input signal is based at least partially on the data sampling clock.