Semiconductor plasma antenna apparatus
View Patent ↗Provided is a semiconductor plasma antenna apparatus. The apparatus includes: a cell array unit in which a plurality of PIN diode cells are arranged, and in which a cell pattern is formed by using a predefined PIN diode cell among the plurality of PIN diode cells; and a driver circuit unit configured to control a drive of the predefined PIN diode cell, wherein the driver circuit unit comprises: a direct-current conversion unit equipped with a DC-DC converter configured to drive a diode load of the cell pattern by applying an output voltage to a PIN diode cell corresponding to the cell patterns formed in the cell array unit; and a constant current controller configured to controlling a plasma concentration of the PIN diode cell by controlling a constant current for the diode load of the cell pattern.
1. A semiconductor plasma antenna apparatus comprising:
a cell array unit in which a plurality of PIN diode cells are arranged, and in which a cell pattern is formed by using a predefined PIN diode cell among the plurality of PIN diode cells; and
a driver circuit unit configured to control a drive of the predefined PIN diode cell, the driver circuit unit comprising a DC-DC converter driving a diode load of the cell pattern by applying an output voltage to the predefined PIN diode cell corresponding to the cell pattern formed in the cell array unit, and a constant current controller controlling a plasma concentration of the predefined PIN diode cell by controlling a constant current for the diode load of the cell pattern,
where the cell array unit comprises a dummy pattern which is formed in an area excluding the cell pattern formed by using the predefined PIN diode cell, and the dummy pattern is connected to ground, and
wherein when a plurality of cell patterns are overlapped with each other, an intrinsic area of a first PIN diode constituting a first pattern among the plurality of cell patterns and an intrinsic area of a second PIN diode constituting a second pattern among the plurality of cell patterns are implemented to be shared with each other.
2. The semiconductor plasma antenna apparatus of claim 1 , wherein the predefined PIN diode cell is connected in series in the cell pattern.
3. The semiconductor plasma antenna apparatus of claim 1 , wherein the predefined PIN diode cell is connected in parallel in the cell pattern.
4. The semiconductor plasma antenna apparatus of claim 1 , wherein, when a single cell pattern is divided into multiple patterns to configure a plurality of diode loads, the number of the PIN diode cells of the plurality of PIN diode cells configuring each diode load is adjusted according to a type of the DC-DC converter.
5. The semiconductor plasma antenna apparatus of claim 1 , wherein the driver circuit unit further comprises a switching unit that intermits a signal between the cell pattern and the DC-DC converter and a signal between the cell pattern and the constant current controller.
6. The semiconductor plasma antenna apparatus of claim 5 , wherein, when the plurality of cell patterns are formed in the cell array unit, the switching unit comprises a switch corresponding to each cell pattern.
7. The semiconductor plasma antenna apparatus of claim 5 , wherein, when a single cell pattern is divided into multiple patterns to configure a plurality of diode loads, the switching unit comprises a switch corresponding to each of the multiple patterns into which the single cell pattern has been divided.
8. The semiconductor plasma antenna apparatus of claim 7 , wherein a length of a corresponding cell pattern is adjusted according to an operation of the switch corresponding to each of the divided patterns.
9. The semiconductor plasma antenna apparatus of claim 5 , wherein the switching unit comprises a logic control circuit that controls an input and output of the plurality of signals.
10. The semiconductor plasma antenna apparatus of claim 1 , wherein the driver circuit unit is mounted on a PCB substrate, and the cell array unit shares a ground plane of the PCB substrate.