Programmable structured arrays
A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
1. A device, comprising:
a plurality of metal wires including a plurality of first metal wires and a plurality of second metal wires; and
a plurality of pass-gates disposed between the plurality of first metal wires and the plurality of second metal wires, wherein the pass-gates are coupled to the plurality of first metal wires through a first plurality of connections and further coupled to the plurality of second metal wires through a second plurality of connections wherein the pass-gates are operable to configure different combinations of connections between the plurality of metal wires, and wherein the different combinations include:
a connection between at least two of only the first metal wires;
a connection between at least two of only the second metal wires; and
a connection between one of the first metal wires and one of the second metal wires;
wherein a combination of the different combinations is configured by turning on a selected combination of the pass-gates.
2. The device of claim 1 , wherein:
the plurality of first metal wires are disposed in a first layer;
the plurality of second metal wires are disposed in a second layer;
the plurality of pass-gates are disposed in a third layer between the first layer and the second layer;
the first plurality of connections comprise via connections that connect the first and third layers; and
the second plurality of connections comprise via connections that connect the second and third layers.
3. The device of claim 1 , wherein the plurality of pass-gates comprise a cross-point matrix of the pass-gates.
4. The device of claim 1 , further comprising a configuration circuit coupled to the plurality of pass-gates and operable for turning respective pass-gates on and off.
5. The device of claim 4 , wherein:
the configuration circuit comprises a first anti-fuse and a second anti-fuse;
if the first anti-fuse is blown, a logic high signal is applied to a respective pass-gate to turn on the pass-gate; and
if the second anti-fuse is blown, a logic low signal is applied to a respective pass-gate to turn off the pass-gate.
6. The device of claim 4 , wherein:
the configuration circuit comprises a floating gate, a transistor, a diode, and a capacitor that couples the floating gate to a control gate;
the device is configured such that a voltage applied to the control gate is coupled to the floating gate through the capacitor and generates a signal to turn on a respective pass-gate; and
the device is further configured such that a voltage applied to the transistor causes charge to be removed from the floating gate through the diode and turns off a respective pass-gate.
7. The device of claim 6 , wherein the configuration circuit further comprises another capacitor coupled between the floating gate and a respective pass-gate.
8. The device of claim 4 , wherein the configuration circuit comprises a type of memory circuit selected from the group consisting of: fuse, EPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating.
9. A device, comprising:
a first layer including first metal wires:
a second layer including second metal wires; and
a third layer disposed between the first and second layers and including an array of pass-gates comprising a cross-point matrix, wherein the array of pass-gates are coupled to the first metal wires through a first plurality of via connections and further coupled to the second metal wires through a second plurality of via connections, wherein each combination of different combinations of connections between the first and second metal wires is configured by turning on a corresponding combination of the array of pass-gates, and wherein the different combinations of connections comprise a connection between:
at least two of only the first metal wires;
at least two of only the second metal wires; and
one of the first metal wires and one of the second metal wires.
10. The device of claim 9 , wherein the array of pass-gates are configured to be turned on and turned off under control of a configuration circuit coupled to the array of pass-gates.
11. The device of claim 10 , wherein the configuration circuit is in the third layer.
12. The device of claim 10 , wherein:
the configuration circuit comprises a first anti-fuse and a second anti-fuse:
if the first anti-fuse is blown, a logic high signal is applied to a respective pass-gate to turn on the pass-gate;
if the second anti-fuse is blown, a logic low signal is applied to a respective pass-gate to turn on the pass-gate.
13. The device of claim 10 , wherein:
the configuration circuit comprises a floating gate, a transistor, a diode, and a capacitor that couples the floating gate to as control gate;
the device is configured such that a voltage applied to the control gate is coupled to the floating gate through the capacitor and generates a signal to turn on a respective pass-gate; and
the device is further configured such that a voltage applied to the transistor causes charge to be removed from the floating gate through the diode and turns off a respective pass-gate.
14. The device of claim 13 , wherein the configuration circuit further comprises another capacitor coupled between the floating gate and the array of pass-gates.
15. The device of claim 10 , wherein the configuration circuit comprises a type of memory circuit selected from the group consisting of: fuse, EPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, demo-magnetic, and resistance modulating.
16. A method of operating a device, the method comprising:
programming, with a configuration circuit, an array of pass-gates including a cross-point matrix in a first layer of the device, wherein said programming comprises turning on a selected combination of the array of pass-gates;
wherein the selected combination from the array of pass-gates electrically connects a combination of a plurality of metal wires, wherein the plurality of metal wires include a plurality of first metal wires in a second layer of the device and a plurality of second metal wires in a third layer of the device, wherein the first layer is sandwiched between the second and third layers, and wherein the combination of metal wires electrically connected according to the selected combination from the array of pass-gates comprises one or more of:
an electrical connection between at least two of only the first metal wires;
an electrical connection between at least two of only the second metal wires; and
an electrical connection between one of the first metal wires and one of the second metal wires.
17. The method of claim 16 , wherein the configuration circuit is in the first layer.
18. The method of claim 16 , wherein:
the configuration circuit comprises a first anti-fuse and a second anti-fuse;
if the first anti-fuse is blown, a logic high signal is applied to a respective pass-gate to turn on the pass-gate; and
if the second anti-fuse is blown, a logic low signal is applied to a respective pass-gate to turn off the pass-gate.
19. The method of claim 16 , wherein:
the configuration circuit comprises a floating gate, a transistor, a diode, and a capacitor that couples the floating gate to a control gate;
a voltage applied to the control gate is coupled to the floating gate through the capacitor and generates a signal to turn on a respective pass-gate; and
a voltage applied to the transistor causes charge to be removed from the floating gate through the diode and turns off a respective pass-gate.
20. The method of claim 19 , wherein the configuration circuit further comprises another capacitor coupled between the floating gate and the array of pass-gates.