Integrated capacitors with nanosheet transistors
A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.
1. A semiconductor device comprising:
a capacitor region and a FET region, wherein the capacitor region is defined by stackedly and alternatingly arranged nanosheets and sacrificial layers disposed on a substrate and the FET region is defined by the stackedly arranged nanosheets,
wherein the nanosheets in the capacitor region have a width and are coupled to one another by the sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width; and
wherein the nanosheets in the FET region are spaced apart and free of sacrificial layers, the nanosheets in the FET region having a width less than half the width of the nanosheets in the capacitor region.
2. The semiconductor device of claim 1 , wherein each one of the nanosheets has a thickness equal to each one of the sacrificial layers.
3. The semiconductor device of claim 1 , wherein the nanosheets comprise silicon and the sacrificial layers comprise silicon-germanium.
4. The semiconductor device of claim 1 , wherein the substrate underlying the capacitor region is conductive, and the stackedly and alternatingly arranged nanosheets and sacrificial layers of the capacitor region are conductively coupled to the substrate.
5. The semiconductor device of claim 1 , wherein the substrate underlying the FET region is free of dopants that make the alternatingly arranged nanosheets and sacrificial layers of the capacitor region conductive.
6. The semiconductor device of claim 1 , wherein the nanosheets and the sacrificial layers have a thickness from 3 nanometers to 30 nanometers.
7. The semiconductor device of claim 1 , wherein the nanosheets in the capacitor region have a width of 25 to 75 nanometers.
8. The semiconductor device of claim 1 , further comprising a high k dielectric material on surfaces of the nanosheets in the capacitor region and the FET region, the sacrificial layers in the capacitor region, and the substrate in the capacitor region.