IP Library Granted Patent US 9,991,250
Granted Patent B2
US 9,991,250 · App. 15/197,889 · Granted Jun 5, 2018

Electrostatic discharge devices and method of making the same

Inventor: T. Jordan Davis (Phoenix, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L27/0248H01L27/0255H01L27/0259H01L27/0292H01L29/866
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Quick Facts
Patent No.
US 9,991,250
App. No.
15/197,889
Granted
Jun 5, 2018
Kind
B2
Abstract

In one embodiment, electrostatic discharge (ESD) devices are disclosed.

Claims (35)

1. An ESD device comprising:

a semiconductor substrate of a first conductivity type;

a first semiconductor region of the first conductivity type, wherein the first semiconductor region overlays substantially all of the semiconductor substrate;

a first doped region of a second conductivity type, wherein the first doped region and the first semiconductor region together form a zener diode;

a second semiconductor region of the second conductivity type disposed on a portion of the first semiconductor region and disposed on a portion of the first doped region, wherein a peak doping concentration of the second semiconductor region is less than a peak doping concentration of the semiconductor substrate;

a second doped region of the first conductivity type disposed in the second semiconductor region and overlying the first doped region, wherein the second doped region is a least two microns apart from the first semiconductor region;

a third doped region of the second conductivity type disposed in the second semiconductor region and overlying the first semiconductor region, wherein the third doped region is spaced at least two microns from the first semiconductor region;

a fourth doped region of the first conductivity type disposed in the second semiconductor region and overlying the third doped region, wherein the third doped region, the fourth doped region, and the first semiconductor region together form a P-N-P junction; and

a first isolation trench extending from a top surface of the second semiconductor region and into the first semiconductor region, wherein the first isolation trench surrounds an outside perimeter of the second doped region and at least a portion of the first doped region, and wherein the first isolation trench does not surround the third doped region or the fourth doped region.

2. The ESD device of claim 1 , wherein the first conductivity type is a P-type conductivity and the second conductivity type is a N-type conductivity.

3. The ESD device of claim 1 , wherein the P-N-P junction has a collector-emitter voltage of about 1 V to about 30 V.

4. The ESD device of claim 1 , wherein the second doped region and the second semiconductor region together form a diode, and wherein a breakdown voltage of the diode is greater than a breakdown voltage for the P-N-P junction.

5. The ESD device of claim 1 , wherein the peak doping concentration of the semiconductor substrate is at least about 1×10 19 atoms/cm 3 .

6. The ESD device of claim 1 , wherein a constant doping concentration of the first semiconductor region is about 1×10 16 atoms/cm 3 to about 1×10 20 atoms/cm 3 .

7. The ESD device of claim 1 , wherein a peak doping concentration of the second doped region is at least about 1×10 19 atoms/cm 3 .

8. The ESD device of claim 1 , wherein a peak doping concentration of the third doped region is at least about 1×10 19 atoms/cm 3 .

9. The ESD device of claim 1 , wherein a peak doping concentration of the fourth doped region is at least about 1×10 19 atoms/cm 3 .

10. The device of claim 1 , further comprising a conductor applied to the second doped region and the fourth doped region.

11. The device of claim 1 , further comprising a conductor applied to the bottom surface of the semiconductor substrate.

12. An ESD device comprising:

a semiconductor substrate of a first conductivity type and having a doping concentration of at least about 1×10 19 atoms/cm 3 ;

a first semiconductor region of the first conductivity having a constant doping concentration of about 1×10 16 atoms/cm 3 to about 1×10 20 atoms/cm 3 , wherein the first semiconductor region overlays substantially all of the semiconductor substrate;

a first doped region of a second conductivity type having a doping concentration of at least about 1×10 19 atoms/cm 3 , wherein the first doped region and the first semiconductor region together form a zener diode;

a second semiconductor region of the second conductivity type disposed on a portion of the first semiconductor region and a portion of the first doped region, wherein the second semiconductor region has a peak doping concentration that is less than peak doping concentration of the semiconductor substrate;

a second doped region of the first conductivity type disposed in the second semiconductor region and overlying the first doped region, wherein the second doped region is a least two microns apart from the semiconductor region, wherein the second doped region has a peak doping concentration of at least about 1×10 19 atoms/cm 3 ;

a third doped region of the second conductivity type disposed in the second semiconductor region and overlying the first semiconductor region, wherein the third doped region is spaced at two microns from the first semiconductor region, and wherein the third doped region has a peak doping concentration of at least about 1×10 19 atoms/cm 3 ;

a fourth doped region of the first conductivity type disposed in the second semiconductor region and overlying the third doped region, wherein the fourth doped region has a peak doping concentration of at least about 1×10 19 atoms/cm 3 ; and

a first isolation trench extending from a top surface of the second semiconductor region and into the first semiconductor region, wherein the first isolation trench surrounds an outside perimeter of the second doped region and a portion of the first doped region, and wherein the first isolation trench does not surround the third doped region or the fourth doped region.

13. The device of claim 1 , wherein the first conductivity type is a P-type conductivity, and the second conductivity type is a N-type conductivity.

14. The device of claim 1 , wherein the first doped region has about the same doping concentration as the second doped region.

15. The device of claim 1 , wherein a doping concentration of the third doped region is less than a doping concentration of the fourth doped region.

16. The device of claim 1 , wherein the semiconductor substrate, the third doped region, and the fourth doped region together form a P-N-P junction in parallel with the zener diode.

17. The device of claim 16 , wherein the P-N-P junction has a collector-emitter voltage of at about 1 V to about 30 V.

18. The device of claim 1 , further comprising a conductor applied to the second doped region and the fourth doped region.

19. The device of claim 1 , further comprising a conductor applied to the bottom surface of the semiconductor substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2016
From: DAVIS, T. JORDAN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 039052/0981 →
Continuity (3)
Provisional Application 62189104 · Jul 6, 2015
Provisional Application 62218829 · Sep 15, 2015
Related Publication 20170012035A1 · Jan 12, 2017