Gate cut on a vertical field effect transistor with a defined-width inorganic mask
A method of cutting a gate on a VFET includes depositing a memorization layer around a spacer on a sidewall of the field effect transistor. A planarizing layer is patterned onto the memorization layer. An anti-reflective coating layer is patterned onto the planarizing layer. A photoresist layer is patterned onto the anti-reflective coating layer on ends of fins extending from a substrate. The planarizing layer, the anti-reflective coating layer, and the photoresist form a mask. The anti-reflective coating layer portion is etched from the VFET. The planarizing layer and the photoresist layer are arc etched from the VFET. The spacer is pulled down forming a void between gates on the VFET and exposing a hard mask on the fins. The hard mask is reactive ion etched vertically around the gates to form gates with a defined width mask. The memorization layer is removed from the VFET.
1. A method of cutting a gate on a vertical field effect transistor (VFET), comprising:
depositing a memorization layer onto the VFET around a spacer on a sidewall of the field effect transistor;
patterning a planarizing layer onto the memorization layer;
patterning an anti-reflective coating layer onto the planarizing layer;
patterning a photoresist layer onto the anti-reflective coating on ends of fins extending from a substrate in the VFET, wherein the planarizing layer, the anti-reflective coating layer, and the photoresist form a mask;
etching the anti-reflective coating layer portion of the mask from the VFET;
arc etching the planarizing layer and the photoresist layer portions of the mask from VFET;
pulling down the spacer forming a void between gates on the VFET and exposing a hard mask on the fins;
reactive ion etching the hard mask by pulling down on the hard mask and reactive ion etching vertically around the gates to form gates with a defined width mask; and
removing the memorization layer from the VFET.
2. The method of claim 1 , wherein the depositing of the memorization layer is done through atomic layer deposition.
3. The method of claim 1 , wherein the memorization layer has a defined width.
4. The method of claim 1 , wherein the memorization layer comprises oxide.
5. The method of claim 1 , wherein the fins are surrounded by an oxide layer.
6. The method of claim 1 , wherein the hard mask on the fins comprises an inorganic hard mask.
7. The method of claim 6 , wherein the hard mask comprises silicon nitride.
8. The method of claim 1 , wherein the gate has a width of 1 nanometer to 50 nanometers.
9. The method of claim 1 , wherein the anti-reflective coating comprises silicon.
10. The method of claim 1 , wherein the photoresist covers the ends of the fins allowing the memorization layer to remain when the mask is etched from the VFET.
11. The method of claim 1 , wherein the reactive ion etching is done vertically across the fins.
12. The method of claim 1 , wherein removing the memorization layer from the VFET includes buffering with an acid to remove the memorization layer.