IP Library Granted Patent US 10,416,900
Granted Patent B2
US 10,416,900 · App. 15/198,015 · Granted Sep 17, 2019

Technologies for addressing data in a memory

Inventors: Jawad B. Khan (Cornelius, OR); Vinodh Gopal (Westborough, MA); Sanjeev N. Trika (Portland, OR)
Assignee: Intel Corporation
G06F3/0613G06F3/061G06F3/064G06F3/068G06F3/0659G06F3/0685
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Quick Facts
Patent No.
US 10,416,900
App. No.
15/198,015
Granted
Sep 17, 2019
Kind
B2
Abstract

Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.

Claims (76)

1. An apparatus comprising:

a controller configured to:

store, in a pointer table in a memory, a sub-block pointer indicative of a location of a first sub-block in a data table;

store, in the data table and in association with the first sub-block, a second pointer that references a first entry where the sub-block pointer is stored in the pointer table;

determine whether a second sub-block to be written to the data table matches the first sub-block;

store, in response to a determination that the second sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a second entry and (ii) a third pointer in association with the first entry, wherein the third pointer is to reference the second entry; and

store, in response to the determination that the second sub-block matches the first sub-block, a fourth pointer in association with the second entry, wherein the fourth pointer references the first entry.

2. The apparatus of claim 1 , wherein the controller is further configured to:

obtain a third sub-block to be written to the data table;

determine whether the third sub-block matches the first sub-block; and

store, in response to a determination that the third sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a third entry and (ii) a fifth pointer in association with the second entry, wherein the fifth pointer is to reference the third entry, and (iii) a sixth pointer in association with the third entry, wherein the sixth pointer is to reference the second entry.

3. The apparatus of claim 1 , wherein the controller is further configured to:

obtain the first sub-block, wherein the first sub-block is to be written to the data table;

generate a hash of the obtained first sub-block;

search the memory for a match of the obtained first sub-block; and

store the obtained first sub-block at a location in the data table in response to a determination that the memory does not include a match for the obtained first sub-block.

4. The apparatus of claim 3 , wherein to search the memory for a match of the obtained first sub-block comprises to:

identify one or more locations in the data table associated with the hash; and

compare data stored at each of the one or more locations to the obtained first sub-block to determine whether the data stored at each location matches the data of the obtained first sub-block.

5. The apparatus of claim 1 , wherein the controller is further configured to:

obtain search data to locate in the memory;

search the data table for a sub-block that matches the search data;

determine, in response to an identification of a sub-block that matches the search data, a pointer to the first entry in the pointer table, wherein the sub-block pointer to the sub-block is stored;

determine a logical address of a block associated with the sub-block pointer; and

add the logical address to a search result set.

6. The apparatus of claim 1 , wherein the controller is further configured to:

obtain search data;

identify a target sub-block in the data table, wherein the target sub-block matches the search data;

identify a target sub-block pointer in the pointer table, wherein the target sub-block pointer is to point to a location of the target sub-block in the data table; and

traverse a linked list of additional sub-block pointers in the pointer table, wherein each sub-block pointer in the linked list is to point to the target sub-block.

7. The apparatus of claim 6 , wherein the linked list is a doubly-linked linked list of pointers.

8. The apparatus of claim 6 , wherein the controller is further configured to:

obtain replacement data;

generate a hash as a function of the replacement data; and

write the replacement data to the data table at a replacement location determined as a function of the hash.

9. The apparatus of claim 8 , wherein the controller is further configured to traverse the linked list and update the sub-block pointers to point to the replacement location.

10. The apparatus of claim 1 , wherein the controller is further configured to set a reference count associated with the location in the data table in response to storage of the sub-block pointer.

11. The apparatus of claim 1 , further comprising one or more of:

at least one processor communicatively coupled to the memory,

a network interface communicatively coupled to a processor,

a display communicatively coupled to a processor, or

a battery coupled to the apparatus.

12. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, when executed, cause an apparatus to:

store, in a pointer table of a memory, a sub-block pointer indicative of a location of a first sub-block in a data table; and

store, in the data table and in association with the first sub-block, a second pointer that references a first entry where the sub-block pointer is stored in the pointer table;

determine whether a second sub-block to be written to the data table matches the first sub-block;

store, in response to a determination that the second sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a second entry and (ii) a third pointer in association with the first entry, wherein the third pointer is to reference the second entry; and

store, in response to the determination that the second sub-block matches the first sub-block, a fourth pointer in association with the second entry, wherein the fourth pointer references the first entry.

13. The one or more non-transitory machine-readable storage media of claim 12 , wherein the plurality of instructions, when executed, further cause the apparatus to:

obtain a third sub-block to be written to the data table;

determine whether the third sub-block matches the first sub-block; and

store, in response to a determination that the third sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a third entry and (ii) a fifth pointer in association with the second entry, wherein the fifth pointer is to reference the third entry, and (iii) a sixth pointer in association with the third entry, wherein the sixth pointer is to reference the second entry.

14. The one or more non-transitory machine-readable storage media of claim 12 , wherein the plurality of instructions, when executed, further cause the apparatus to:

obtain the first sub-block, wherein the first sub-block is to be written to the data table;

generate a hash of the obtained first sub-block;

search the memory for a match of the obtained first sub-block; and

store the obtained first sub-block at a location in the data table in response to a determination that the memory does not include a match for the obtained first sub-block.

15. The one or more non-transitory machine-readable storage media of claim 14 , wherein to search the memory for a match of the obtained first sub-block comprises to:

identify one or more locations in the data table associated with the hash; and

compare data stored at each of the one or more locations to the obtained first sub-block to determine whether the data stored at each location matches the data of the obtained first sub-block.

16. The one or more non-transitory machine-readable storage media of claim 12 , wherein the plurality of instructions, when executed, further cause the apparatus to:

obtain search data to locate in the memory;

search the data table for a sub-block that matches the search data;

determine, in response to an identification of a sub-block that matches the search data, a pointer to the first entry in the pointer table, wherein the sub-block pointer to the sub-block is stored;

determine a logical address of a block associated with the sub-block pointer; and

add the logical address to a search result set.

17. A method comprising:

storing, by a controller of an apparatus and in a pointer table, a sub-block pointer indicative of a location of a first sub-block in a data table;

storing, by the controller and in the data table, in association with the first sub-block, a second pointer that references a first entry where the sub-block pointer is stored in the pointer table;

determining, by the controller, whether a second sub-block to be written to the data table matches the first sub-block;

storing, by the controller and in response to a determination that the second sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a second entry and (ii) a third pointer in association with the first entry, wherein the third pointer is to reference the second entry; and

storing, by the controller and in response to the determination that the second sub-block matches the first sub-block, a fourth pointer in association with the second entry, wherein the fourth pointer references the first entry.

18. The method of claim 17 , further comprising:

obtaining, by the controller, a third sub-block to be written to the data table;

determining, by the controller, whether the third sub-block matches the first sub-block; and

storing, by the controller and in response to a determination that the third sub-block matches the first sub-block, (i) the sub-block pointer in the pointer table in a third entry and (ii) a fifth pointer in association with the second entry, wherein the fifth pointer is to reference the third entry, and (iii) a sixth pointer in association with the third entry, wherein the sixth pointer is to reference the second entry.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072915/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2016
From: KHAN, JAWAD B.; GOPAL, VINODH; TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 039075/0158 →
Continuity (1)
Related Publication 20180004434A1 · Jan 4, 2018