IP Library Granted Patent US 9,984,968
Granted Patent B2
US 9,984,968 · App. 15/198,799 · Granted May 29, 2018

Semiconductor package and related methods

Inventors: Yusheng Lin (Phoenix, AZ); Yenting Wen (Chandler, AZ); George Chang (Tempe, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/528H01L21/304H01L21/50H01L21/78H01L23/36H01L23/5228H01L23/53228
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Quick Facts
Patent No.
US 9,984,968
App. No.
15/198,799
Granted
May 29, 2018
Kind
B2
Abstract

Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Claims (28)

1. A method of making a semiconductor package, the method comprising:

providing a wafer comprising a first side comprising a plurality of metal oxide semiconductor field effect transistors (MOSFETs);

grinding a second side of the wafer to bring the wafer to a predetermined thickness between the first side and the second side;

forming a back side metallization on the second side of the wafer;

singulating the plurality of MOSFETs into one or more die that each comprise at least two MOSFETs;

forming a plurality of semiconductor packages by coupling the one or more die to an electrically conductive section using an electrically conductive material, the electrically conductive section having a predetermined thickness;

curing the electrically conductive material; and

singulating the plurality of semiconductor packages by one of punching or stamping the electrically conductive section;

wherein, during operation of the die, the at least two MOSFETs are electrically coupled through the electrically conductive section.

2. The method of claim 1 , further comprising reducing the on-resistance of the at least two MOSFETs through the coupling of the electrically conductive section to the back metal.

3. The method of claim 1 , wherein the electrically conductive section is formed independently from the back metal during processing of the wafer.

4. The method of claim 1 , wherein the predetermined thickness of the electrically conductive section is between 25 microns and 125 microns.

5. The method of claim 1 , wherein the electrically conductive section comprises one of copper, aluminum, silver, gold, titanium, and any combination thereof.

6. The method of claim 1 , wherein the electrically conductive section comprises copper.

7. The method of claim 1 , wherein the electrically conductive material is one of a silver sintering paste, solder, electrically conductive epoxy, and any combination thereof.

8. The method of claim 1 , wherein the back metal comprises a titanium, nickel and silver alloy.

9. A method for making a semiconductor package, the method comprising:

providing a sheet of electrically conductive material of a predetermined thickness;

punching a plurality of electrically conductive sections from the sheet;

providing a wafer comprising a plurality of MOSFETs on a first side of the wafer;

thinning a thickness of the wafer;

applying a back side metallization on a second side of the wafer;

coupling a plurality of electrically conductive sections to a second side of the wafer, each electrically conductive section coupled to two or more of the plurality of MOSFETs;

singulating each electrically conductive section and a two or more MOSFETs of the plurality of MOSFETs coupled thereto to form a plurality of semiconductor packages; and

electrically coupling through the electrically conductive section the two or more MOSFETs during operation of each of the plurality of semiconductor packages.

10. The method of claim 9 , further comprising reducing the on-resistance of the two or more MOSFETs through the coupling of the electrically conductive section to the back metal.

11. The method of claim 9 , wherein the electrically conductive section is not formed as part of the back metal during processing of the wafer.

12. The method of claim 9 , wherein the predetermined thickness of the electrically conductive section is between 25 microns and 125 microns.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: LIN, YUSHENG; WEN, YENTING; CHANG, GEORGE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 039262/0688 →
Continuity (1)
Related Publication 20180005936A1 · Jan 4, 2018