IP Library › Granted Patent US 10,429,439
Granted Patent B2
US 10,429,439 · App. 15/201,315 · Granted Oct 1, 2019

In die stepping sort

Inventors: Dae-Woo Kim (Phoenix, AZ); J. Daniel Bryan (Aloha, OR); Joseph W. Parks, Jr. (Aloha, OR); Ethan Caughey (Hillsboro, OR); Mark W. Dryfuse (Hillsboro, OR)
Assignee: Intel Corporation
G01R31/2886G01R1/07378G01R31/2601G01R31/2889H01L23/5386
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Quick Facts
Patent No.
US 10,429,439
App. No.
15/201,315
Granted
Oct 1, 2019
Kind
B2
Abstract

An apparatus for testing a die can comprise a first printed circuit board (PCB), a space transformer, and a plurality of probes. The first PCB can be configured to connect to a second PCB. The space transformer can be attached to the PCB. The space transformer can include a plurality of traces. Each of the plurality of probes can be connected to one of the plurality of traces.

Claims (39)

1. An apparatus for testing a plurality of dies, each of the plurality of dies having a plurality of bumps, the apparatus comprising:

a test head having a plurality of probes, each of the plurality of probes connected to one of a plurality of traces of a space transformer, the plurality of probes arranged in a pattern having a pitch less than 65 microns;

a processor; and

a memory storing instructions that, then executed by the processor, cause the processor to:

actuate the test head such that the plurality of probes contact a subset of the first plurality of bumps of one of the plurality of dies, and

receive a voltage signal from the plurality of probes when the plurality of probes is in contact with the subset of the plurality of bumps of the one of the plurality of dies, wherein the plurality of dies is an embedded multi-die interconnect bridge.

2. The apparatus of claim 1 , further comprising at least one guide plate arranged to reinforce the plurality of probes.

3. The apparatus of claim 1 , wherein each of the plurality of probes has a length ranging from about 0.25 mm to about 2 mm.

4. The apparatus of claim 1 , further comprising a conveyer configured to reposition each of the dies proximate the test head.

5. The apparatus of claim 1 , further comprising a second test head having a second plurality of probes, each of the second plurality of probes connected to one of a second plurality of traces of a second space transformer, the second plurality of probes arranged in a second pattern having a second pitch less than 65 microns, the second pattern corresponding to a second subset of the plurality of bumps of the one of the plurality of dies.

6. A method of testing a plurality of dies having a plurality of bumps, the method comprising:

contacting a first subset of the plurality of bumps with a plurality of probes of a test head including the plurality of probes arranged in a pattern having a pitch less than 65 microns;

transmitting, via the test head, a test signal through each of a plurality of traces within the die;

receiving, at a computing device from the test head, a return signal indicating a continuity state of a plurality of traces, each of the plurality of traces connecting a pair of bumps of the subset of bumps; and

contacting a second subset of bumps with a second plurality of probes of a second test head, the second plurality of probes arranged in a second pattern having a second pitch less than 65 microns, the second pattern corresponding to a second subset of the plurality of bumps.

7. The method of claim 6 , further comprising applying a test current across each of the pair of bumps.

8. The method of claim 6 , wherein receiving the signal includes detecting a voltage signal at each of the pair of bumps of the subset of bumps.

9. The method of claim 6 , further comprising contacting a second subset of bumps, the second subset of bumps having a pattern that is the same as the pattern of the subset of bumps.

10. An apparatus for testing a plurality of dies, each of the plurality of dies having a plurality of bumps, the apparatus comprising:

means for contacting a subset of the plurality of humps of one of the plurality of dies, the contacting means including a plurality of probes arranged in a pattern having a pitch less than 65 microns; and

means for receiving a test signal from the contacting means when the contacting means is in contact with the subset of the plurality of bumps,

wherein the plurality of dies is an embedded multi-die interconnect bridge.

11. The apparatus of claim 10 , further comprising means for reinforcing the plurality of probes.

12. The apparatus of claim 10 , wherein each of the plurality of probes has a length ranging from about 0.25 mm to about 2 mm.

13. The apparatus of claim 10 , further comprising means for repositioning the subset of the plurality of bumps of each of the plurality of dies proximate the means for contacting the subset of the plurality of bumps.

14. The apparatus of claim 10 , further comprising a second means for contacting a second subset of the plurality of bumps, the second contacting means including a second plurality of probes arranged in a second pattern having a second pitch less than 65 microns, the second pattern corresponding to the second subset of the plurality of bumps of the one of the plurality of dies.

15. An apparatus for testing a plurality of dies, each of the plurality of dies having a plurality of bumps, the apparatus comprising:

a first test head having a first plurality of probes, each of the first plurality of probes connected to one of a first plurality of traces of a first space transformer, the first plurality of probes arranged in a first pattern having a first pitch less than 65 microns;

a second test head having a second plurality of probes, each of the second plurality of probes connected to one of a second plurality of traces of a second space transformer, the second plurality of probes arranged in a second pattern having a second pitch less than 65 microns, the second pattern corresponding to a second subset of the plurality of bumps of the one of the plurality of dies;

a processor; and

a memory storing instructions that, when executed by the processor, cause the processor to:

actuate the first test head such that the first plurality of probes contact a first subset of the first plurality of bumps of one of the plurality of dies,

receive a first voltage signal from the first plurality of probes when the first plurality of probes is in contact with the first subset of the plurality of bumps of the one of the plurality of dies,

actuate the second test head such that the second plurality of probes contact a second subset of the second plurality of bumps of one of the plurality of dies, and

receive a second voltage signal from the second plurality of probes when the second plurality of probes is in contact with the second subset of the plurality of bumps of the one of the plurality of dies.

16. The apparatus of claim 15 , further comprising at least one guide plate arranged to reinforce the plurality of probes.

17. The apparatus of claim 15 , wherein each of the plurality of probes has a length ranging from about 0.25 mm to about 2 mm.

18. The apparatus of claim 15 , further comprising a conveyer configured to reposition each of the dies proximate the test head.

19. The apparatus of claim 15 , wherein the die is an embedded multi-die interconnect bridge.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2017
From: DRYFUSE, MARK W; CAUGHEY, ETHAN; PARKS, JOSEPH W, JR; BRYAN, J DANIEL; KIM, DAE-WOO
To: INTEL CORPORATION
Reel/Frame 042532/0702 →
Continuity (1)
Related Publication 20180003765A1 · Jan 4, 2018